Principal RFIC Design Engineer
Mountain View, CA · HybridJobPosted 4mo agoStill listed 4 days ago
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Job overview
Oso Semiconductor is hiring a Principal RFIC Design Engineer. Oso Semiconductor is seeking a Principal RFIC Design Engineer to join its core design team. This senior technical role involves designing, simulating, and validating mmWave front-end circuit blocks for next-generation beamformer chips. The engineer will contribute to architecture decisions and see designs through from schematic to silicon and customer products.
Key focus areas include Design mmWave front-end circuit blocks in advanced CMOS or RFSOI, Perform transistor-level schematic design, simulation, and optimization, and Conduct full-custom IC layout or direct layout engineers.
Successful candidates bring MS Plus 5 Years Industry Experience, PhD Plus 2 Years Industry Experience, and Expertise In Two Of PA LNA Phase Shifter VGA Mixer. Important skills include RFIC Design, mmWave Front-End Circuit Blocks Design, LNA Design, PA Design, Phase Shifter Design, and VGA Design. Preferred (not required): Phased Array IC Design, Multi-Channel Beamformer IC Design, SATCOM mmWave Applications, and 5G NR FR2 mmWave Applications.
Skills & qualifications
Skills
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Full job description
About Oso Semiconductor
Oso Semiconductor is an early-stage fabless semiconductor company developing next-generation mmWave beamforming technology. Founded by UC Berkeley PhDs, our proprietary RFIC architecture delivers 2–4x power reduction for phased array systems across satellite communication (SATCOM), 5G, and radar. We’ve raised Series A funding, secured our first defense and commercial customers, and are preparing to scale the team 3X.
The Role
We’re looking for a Principal RFIC Design Engineer to join the core design team. You’ll design, simulate, and validate mmWave front-end circuit blocks for our next-generation beamformer chips—including LNAs, PAs, phase shifters, VGAs, and complete transceiver signal chains.
This is a senior technical role with significant design ownership. You’ll work directly with the founding engineers, contribute to architecture decisions, and see your designs go from schematic to silicon to customer products.
Responsibilities
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Design mmWave front-end circuit blocks (PAs, LNAs, phase shifters, VGAs, mixers) in advanced CMOS or RFSOI (SiGe and III-V processes are a plus).
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Perform transistor-level schematic design, simulation, and optimization using Cadence Virtuoso (Spectre, ADE).
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Conduct full-custom IC layout or direct layout engineers, ensuring DRC/LVS-clean designs at mmWave frequencies.
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Perform post-layout extraction and EM simulation (Ansys HFSS, EMX, ADS Momentum) to validate performance through parasitics.
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Collaborate on chip-level architecture and system partitioning for multi-channel beamformer ICs.
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Support silicon bring-up, bench characterization, and debugging of fabricated chips.
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Contribute to tapeout preparation, design reviews, and documentation.
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Mentor junior RFIC designers and contribute to a culture of technical excellence. Required Qualifications
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MS + 5 years industry experience or PhD + 2 years industry experience in Electrical Engineering with a focus on RF/mmWave IC design.
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Demonstrated expertise in at least two of: PA, LNA, phase shifter, VGA, mixer, or frequency multiplier design at mmWave frequencies.
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Expert proficiency with Cadence EDA suite (Virtuoso, ADE, and Layout) and EM simulation tools (Ansys HFSS, EMX, or ADS Momentum).
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Experience with at least one full tapeout cycle: schematic to layout to fabrication to bring-up to characterization.
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Strong understanding of mmWave transmission line theory, matching networks, and on-chip passive design.
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Track record of published work or shipped products demonstrating circuit design excellence. Preferred Qualifications
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Experience with phased array or multi-channel beamformer IC design.
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Background in SATCOM, 5G NR FR2, or automotive radar mmWave applications.
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Experience in SOI nodes with high resistivity substrates.
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Familiar with system-level RF specs: EVM, P1dB, noise figure, IP3, EIRP, and G/T.
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Experience in a startup or small-team environment with high design ownership.
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Strong communication skills and ability to present design tradeoffs clearly. Why Oso Semi?
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Design ownership: You own blocks from concept to silicon.
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Small team: Your voice matters in every architecture decision.
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Cutting-edge process: Advanced nodes for mmWave—the hardest corner of IC design.
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Meaningful equity: Competitive stock option grant. Early engineers capture real value.
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UC Berkeley DNA: Founded by PhDs published in IEEE conferences and journals.
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First Principles Innovation: Multiple patents providing 2-4x reductions in power.
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Established Traction: Signed multi-year, high-volume customer agreements in defense and commercial markets (SATCOM, radar, and 5G). What We Offer
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Equity: Stock option grant with 4-year vesting and 1-year cliff.
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Medical, Dental & Vision: Comprehensive health coverage with employer-sponsored medical, dental, and vision plans.
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Hybrid Schedule: Monday–Wednesday in office.
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Time Off: Unlimited PTO.
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401(k): Employer-matched retirement plan.
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Team Culture: Regular team lunches, events, and celebrations.
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Life Insurance: Company-paid life insurance.
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FSA & HSA: Flexible spending and health savings account options available.
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Commuter Benefits: Pre-tax transit and parking benefits.
Oso Semiconductor is an equal opportunity employer. We consider all qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic.
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