Principal Design Verification Engineer (Design or DV)

Technically lead A Subsystem as a design or DV engineer. Collaborate across teams on vertical and horizontal reuse of components. Provide technical leadership through mentorship and strong teamwork. Work effectively with Architecture, Design, DV, PD, DFT, firmware, and post-silicon teams to debug system-level issues and deliver silicon from concept through bring-up. Understanding of many of the following: complex subsystems (such as PCIE, HBM, imaging or control), fabrics, AMBA AXI/CHI protocols, DMA engines, NoCs, and high-throughput data buffering and movement. Design includes but not limited to - Bandwidth, latency, utilization, and power tradeoffs while driving synthesis, timing constraints, floor-planning awareness, and performance tuning (Design). Expertise in design or DV domains, especially on memory technologies. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Experience debugging Register Transfer Level (RTL) designs as well as simulation and/or emulation environments. Experience with design quality and static checks, DFT implementation and hand off to physical design. Expertise in design or DV domains Experience with verification for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM). Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs Experience in Scripting language such as Python or Perl