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Principal RFIC Design Engineer - Chip Lead

Oso Semiconductor

Mountain View, CAJobPosted 1w agoStill listed 1w ago

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At a glance

Compensation
No compensation found
Location
Mountain View, CA
Work Authorization
Not specified

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Job overview

We’re looking for a Principal RFIC Design Engineer – Chip Lead to own top‑level integration of next‑generation multi‑channel beamformer ICs, driving architecture, floorplanning, performance and tapeout readiness while collaborating with founding engineers and block owners to deliver a manufacturable, testable product.

Skills & qualifications

RequiredNice to have

Skills

RFIC DesignChip ArchitectureFloorplanningBlock IntegrationRF/Analog PerformancePhysical ImplementationPackage InterfacesTapeoutSilicon Bring‑Up

Full job description

We’re looking for a Principal RFIC Design Engineer - Chip Lead to own top-level integration of our next-generation multi-channel beamformer ICs. You’ll drive chip architecture, floorplanning, block integration, top-level RF/analog performance, physical implementation, package interfaces, and tapeout readiness across RF, analog, digital, layout, and test functions. This is a senior technical leadership role for an experienced IC designer who can see the whole chip. You’ll work directly with the founding engineers and block owners to turn system requirements into a manufacturable, testable product and drive execution from architecture and floorplan through sign-off, silicon bring-up, and customer deployment.

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