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Sr. Manager, Post-Silicon Eng, AWS Hardware Engineering Services

Amazon

Seattle, WAJob$198–268K/yrSeen 2w agoSeen in employer's feed 2 days ago

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At a glance

Compensation
$198–268K/yr
Location
Seattle, WA
Work Authorization
Not specified

Olive lists jobs from US employers, including remote roles you can work from the United States.

Requirements

Credentials this posting asks for.

Bachelor's degree

Job overview

Amazon Web Services is seeking a Senior Manager to lead engineering teams responsible for post-silicon validation and fleet operations across server hardware. The organization spans PCIe validation and signal integrity, CPU and memory quality, server performance, and test automation. The role owns technical outcomes from silicon bring-up through production deployment, including fleet issue response, corrective action, and ongoing operational health.

Skills & qualifications

RequiredNice to have

Skills

Post-Silicon ValidationSilicon Bring-UpPlatform ValidationFleet EngineeringEngineering ManagementServer Processor DebugCPU ValidationMemory ValidationHigh-Speed InterconnectPCIe Signal IntegritySerDes CharacterizationCompliance TestingLink Training DebugFirmware ValidationSoftware ValidationDriver-Level TestingProtocol-Level TestingTest AutomationServer Performance CharacterizationMemory Bandwidth AnalysisLatency AnalysisCPU Microarchitecture AnalysisRoot-Cause AnalysisCorrective ActionTeam Scaling

Qualifications

Bachelor's in Computer Science or Related Field10+ Years Post-Silicon or Related Experience5+ Years Engineering Management Experience2+ Years Managing ManagersMaster's or PhD in Electrical Engineering, Computer Engineering, or Related Field

Benefits

Medical Insurance
Dental Insurance
Vision Insurance
401(k) Match
Paid Time Off
Parental Leave

Full job description

Description

Amazon Web Services designs and builds the servers and custom silicon that power the world's largest cloud. The Core Hardware team owns the cross-cutting engineering capabilities that every server product depends on: power delivery, PCIe connectivity, signal integrity, CPU and memory quality, board design, thermal and mechanical systems, and the test and quality infrastructure that validates and sustains all of it.

We are looking for a Senior Manager to lead engineering teams within Core Hardware. This is a manager-of-managers role. Your organization owns PCIe validation and signal integrity, CPU and memory quality engineering, server performance, and test automation infrastructure. These teams are responsible not only for validating that every server platform meets the highest bar for silicon quality, interconnect reliability, and system performance before production, but also for owning the ongoing quality and operational health of those subsystems once they are deployed in the fleet.

This is a technical leadership role with real depth and end-to-end ownership. Your teams operate at the intersection silicon, servers and the fleet, and that boundary does not disappear at production release. They validate PCIe connectivity at the physical and protocol layer, find and resolve bugs in shipped silicon, characterize server performance at scale, build the automation infrastructure that makes all of this repeatable, and then own the outcomes when those platforms are running in production. When a fleet-wide issue surfaces that traces back to silicon, interconnect, or memory behavior, your organization owns the response: root cause, corrective action, and the systemic fix that prevents recurrence. The right leader for this role brings deep fluency in post-silicon validation and uses that fluency to drive outcomes across the full lifecycle, from first silicon through fleet operations.

Key job responsibilities

  • Own the end-to-end technical output and operational health of engineering teams spanning PCIe validation and signal integrity, CPU and memory engineering, server performance, and test automation, from silicon bring-up through fleet deployment and ongoing operations.

  • Lead first-line managers and set the technical direction for validation methodology and fleet engineering, ensuring that validation plans, coverage models, debug workflows, and production monitoring strategies reflect the complexity of Amazon's custom server platforms and silicon.

  • Build the processes and tooling that connect what your teams learn in validation to how they operate in the fleet, closing the loop between pre-production findings and production outcomes.

  • Drive root-cause analysis and corrective action for issues that surface at any point in the lifecycle, whether during bring-up, qualification, or in the production fleet. When a fleet-wide issue traces back to silicon, interconnect, or memory behavior, your organization owns the technical response end-to-end: diagnosis, root cause, fix, and the systemic improvement that prevents recurrence.

  • Partner with silicon suppliers, firmware, and hardware design teams to drive cross-functional resolution of platform-level issues that span silicon, firmware, board, and operational boundaries.

  • Represent your organization's technical findings, fleet health posture, and risk assessments to senior leadership with the depth and clarity expected at the director level and above, translating complex silicon and platform data into actionable decisions for product teams, fleet operations, and architecture teams.

  • Build and develop a team of managers engineers who think beyond validation and own outcomes in the fleet, developing the institutional knowledge and end-to-end mindset that Amazon's ownership model demands.

Basic Qualifications

  • Bachelor's degree in Computer Science or a related field

  • 10+ years of experience in post-silicon validation, silicon bring-up, platform validation, or fleet engineering for server-class hardware.

  • 5+ years of engineering management experience with direct people management responsibility.

  • 2+ years of experience managing managers, not just individual contributors.

  • Direct technical experience with server-class processor debug and validation, including CPU, memory, and high-speed interconnect subsystems such as PCIe, spanning both pre-production validation and production fleet operations.

  • Experience owning engineering outcomes across the full product lifecycle, from silicon bring-up through production deployment and ongoing fleet operations, not limited to a hand-off at production release.

Preferred Qualifications

  • Experience with PCIe physical layer signal integrity, including SerDes characterization, compliance testing, and link training debug in both lab and fleet environments.

  • Experience with firmware and software validation in a post-silicon environment, including driver-level and protocol-level test development that carries forward into production monitoring and regression.

  • Experience building or leading teams that develop test automation infrastructure, frameworks, and tooling used across both validation and fleet-facing engineering workflows.

  • Experience with server performance characterization, including memory bandwidth, latency, and CPU microarchitecture-level performance analysis, with the ability to translate findings into fleet-level operational decisions.

  • Experience driving root-cause analysis and corrective action for hardware issues discovered in production fleets at scale, including coordination with silicon vendors, firmware teams, and fleet operations.

  • Experience hiring and scaling engineering teams, particularly in competitive talent markets or during site buildouts.

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits .

USA, WA, Seattle - 197,900.00 - 267,800.00 USD annually

How this job compares

Set against the 2,265 open Engineering Management jobs on Olive Jobs, counted November 7, 2026.

Pay
  • This posting$198–268K/yr
  • Washington median$172–270K/yr74 salary ranges
  • US median$146–264K/yr1,843 salary ranges

This range's midpoint, $233K, is 6% above the Washington median midpoint ($221K) — in the middle half of Engineering Management salary ranges in Washington.

Openings
Olive Jobs lists 81 open Engineering Management jobs in Washington and 2,265 across the US. 7% of them nationwide are listed as remote or flexible.
Hiring the most in Washington
Experience
This posting asks for at least 10 years of experience; Engineering Management postings that state a minimum ask for 8 years at the median (1,919 postings).
Education
This posting asks for a bachelor's degree; 854 of the 2,265 open Engineering Management jobs (38%) ask for a bachelor's degree or higher.

Counted across the open, public US postings on Olive Jobs on November 7, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.

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