Principal Silicon Security Architect

The candidate for this position will be expected and able to complete the following responsibilities: Lead end-to-end security architecture for complex SoCs and silicon subsystems from product requirements and threat analysis through architecture signoff, implementation, validation, production, and post-silicon issue resolution. Define the SoC security framework, trust boundaries, security objectives, assets, attacker models, and hardware, firmware, and software responsibilities. Lead threat modeling and security risk assessments covering hardware, firmware, software, microarchitectural, supply-chain, lifecycle, and physical attack surfaces; drive mitigations and residual-risk closure. Architect hardware roots of trust, secure and measured boot, device identity and attestation, key management, secure provisioning, ownership transfer, lifecycle states, secure recovery, and firmware update mechanisms. Define isolation and confidential-computing architecture, including security enclaves or trusted execution environments, memory and I/O protection, access control, privilege boundaries, virtualization, and multi-tenant security. Define secure debug, telemetry, error handling, anti-rollback, tamper response, and manufacturing and field-service security requirements while preserving product diagnosability and supportability. Define cryptographic services and acceleration requirements; evaluate algorithms, protocols, key hierarchies, entropy sources, and implementation tradeoffs for performance, power, area, assurance, and agility. Assess side-channel, fault-injection, replay, rollback, and other physical or microarchitectural threats; partner with design and validation teams on mitigations and security test strategies. Author clear, testable security requirements and architecture specifications, maintain requirements traceability, and establish review, verification, validation, and signoff criteria. Evaluate internal and third-party security IP and vendor solutions; lead architecture reviews and provide data-driven recommendations spanning security assurance, functionality, PPA, cost, schedule, reuse, and risk. Drive cross-functional and cross-company technical alignment, resolve ambiguous or conflicting security requirements, and influence product and platform direction at Principal scope. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 15+ years technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience. Experience architecting security for data-center, cloud, client, gaming, AI accelerator, infrastructure accelerator, or server-class SoCs. Knowledge of hardware roots of trust, security enclaves, trusted execution environments, confidential computing, secure and measured boot, attestation, secure recovery, and secure firmware update. Knowledge of cryptographic algorithms, protocols, key hierarchies, entropy generation, crypto agility, and hardware security modules or TPM-class technologies. Experience with device identity, secure provisioning, manufacturing security, ownership transfer, lifecycle management, anti-rollback, access control, and secure debug. Experience analyzing and mitigating side-channel attacks, fault injection, physical attacks, microarchitectural threats, or supply-chain threats. Experience with memory and I/O protection, IOMMU/SMMU, virtualization, privilege separation, multi-tenant isolation, or secure DMA architectures. Experience defining security verification and validation strategies, including negative testing, penetration testing, emulation, formal methods, fuzzing, or post-silicon security validation. Experience with applicable security standards or certification programs such as FIPS 140-3, CNSA, TCG, DICE, SPDM, or Common Criteria. Experience evaluating third-party security IP and working with external silicon vendors or semiconductor partners through architecture, design, verification, and productization. Experience architecting networking or high-speed I/O subsystems, including hands-on experience with network data paths and/or packet-processing architectures. Experience with PCI Express (PCIe) architecture, integration, or design, including link capabilities, topology, error handling, power/reset flows, hardware/firmware/software interactions and trusted computing via PCIe TDISP/IDE. Experience applying AI-assisted tools to architecture research, specification development, requirements analysis, or engineering productivity.