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Layout/Mask Designer

Apple

Multiple U.S. locationsFull-timeSeen 1 day agoSeen in employer's feed 1 day ago

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At a glance

Compensation
No compensation found
Location
Multiple U.S. locations
Schedule
Full-time
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

Master's degree

Job overview

Apple seeks a Layout/Mask Designer to create complex custom layouts for digital circuits in deep-submicron CMOS technologies. The role works with circuit designers on floorplans, schedules, and layout tradeoffs; uses verification and automated place-and-route tools; and analyzes reports and simulations to improve manufacturability, performance, and power delivery. The position is based in Beaverton, Oregon, and is scheduled for 40 hours per week.

Skills & qualifications

RequiredNice to have

Skills

Layout Floor PlanningStandard Cell PlanningHierarchical Layout AssemblyWire PlanningRC Delay AnalysisElectromigration AnalysisSelf-Heating AnalysisCross-Capacitance AnalysisLayout Failure RecognitionPower Grid DesignIR SimulationDRC and LVS AnalysisCadence VirtuosoLow-Noise Data Path DesignLow-Power Data Path DesignMemory Layout Design

Qualifications

Master's in Electrical, Computer, Electronics Engineering or Related Field2 Years Related Experience

Full job description

Weekly Hours: 40

Role Number: 200691672-0505

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Beaverton, Oregon. Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies. Reviewing and analyzing floorplans and complex circuits with circuit designers. Running a complete set of layout design verification tools available on megacells completed. Working with the circuit design team to plan, schedule work and negotiate layout tradeoffs as needed. Analyzing of LVS, DRC and ERC reports to find the fastest way to complete layouts. Utilizing advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Utilizing advanced layout techniques to come up with best in class PPA for critical designs. Performing EMIR simulations and apply necessary fixes to achieve robust power delivery. Reviewing the layouts designed by peers and provide improvement recommendations. Utilizing automated P&R tools to speed up the layout execution of digital designs. 40 hours/week.

Minimum Qualifications

  • Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, Electronics Engineering or related field and 2 years of experience in the job offered or related occupation.

  • 2 years of experience with each of the following skills is required:

  • Utilizing knowledge in layout floor-planning, standard cell planning & hierarchical layout assembly.

  • Applying understanding of issues with RC delay, electro migration, self-heating & cross capacitance to perform optimal wire planning.

  • Recognizing prone layout structures failure and collaborating with other designers to identify solutions.

  • Designing and validating a robust power grid using IR simulation tools to avoid failure prone networks.

  • Interpreting DRC & LVS reports to build manufacturable layout.

  • Utilizing knowledge of cadence virtuoso layout design tools for designing layout structures.

  • Utilizing circuit and layout knowledge in creating low noise, low power data paths and/or memory layout structures.

Preferred Qualifications

  • N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.

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