Memory Design Engineer

Job Details:

Job Description: Role Overview You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel's advanced CMOS process technologies.

Business Group The Advanced Design (AD) team is part of Intel’s larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel’s internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel’s advanced CMOS process technologies.

In this position your responsibilities will include, but may not be limited to:

• Define, develop, and optimize advanced memory bitcells, array architectures, and peripheral circuits.
• Lead memory pathfinding and optimize power, performance, and area (PPA) through design-technology co-optimization (DTCO) and product design enablement.
• Develop and validate memory libraries for PDK enablement across Intel's advanced process technologies.
• Design memory arrays and IP, develop innovative memory circuits, and execute and validate test chips.

Your contributions will directly enable leading-edge products with high-performance, high-density, low-power memory implemented on Intel's advanced CMOS process technologies.

Qualifications: Minimum Qualifications

• BA degree with 3 years of experience or Master's degree in Electrical Engineering, Computer Engineering, or a related STEM field with 2+ years of experience OR a PhD with no experience.
• Experience in customer circuit design, simulation, layout design and verification.
• Hands-on experience with relevant industry EDA tools and flows for digital and/or analog design and verification, such as Cadence Virtuoso, Synopsys StarRC, and Synopsys HSPICE.

Preferred Qualifications

• Experience in memory bitcell and circuit design.
• Experience with advanced CMOS process technologies and device physics.
• Experience evaluating and balancing power, performance, and area trade-offs.
• Experience designing, characterizing, and verifying custom memory circuits, such as SRAM, register files, and ROM.
• Experience optimizing the physical design of custom circuits.

Job Type: College Grad

Shift: Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations: US, California, Santa Clara, US, Texas, Austin

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.