Principal Signal Power Integrity Engineer, Texas Institute for Electronics
Austin, TXJobSeen 2w agoSeen in employer's feed 4 days ago
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Job overview
The Principal Signal Power Integrity Engineer will lead signal integrity and power integrity analysis for advanced 2.5D and 3.0D heterogeneous integration packages, from interconnect architecture through silicon-package co-design and signoff. The role develops and validates reusable models and simulation flows, incorporates next-generation interface standards into design methodology, and guides technical strategy while mentoring engineers and representing TIE with industry partners and customers.
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Full job description
Own and drive signal integrity and power integrity (SI/PI) analysis end-to-end for advanced 2.5D/3.0D heterogeneous integration packagesfrom initial interconnect architecture through silicon-package co-design to final signoff.Perform high-speed interconnect modeling and extraction (S-parameters, RLCK, transmission-line models) across TSVs, micro-bumps, hybrid bonds, RDL, and advanced substrates (silicon, glass, organic).Architect and optimize power delivery networks (PDN) for multi-chiplet 3D stacksincluding target impedance analysis, decoupling strategy, IR-drop simulation, and PDN resonance identification from die through package to board.Execute full SI simulation workflows: EM extraction, crosstalk analysis, eye diagram/BER prediction, channel compliance simulation, and jitter budgeting for high-speed interfaces (PCIe Gen6/7, CXL, UCIe, SerDes, HBM).Build and validate SI/PI models for the 3D Assembly Design Kit (ADK)creating accurate, reusable electrical models that enable chiplet designers to perform system-level co-design against TIEs integration platform.Develop reference flows, scripts, and automation that make SI/PI enablement repeatable and accessible to internal design teams and external customers.Collaborate directly with EDA vendors (Cadence, Ansys, Synopsys, Siemens, Keysight), OSATs, and foundries to develop, benchmark, and refine package-level SI/PI simulation flows and tool interoperability.Track and incorporate requirements from next-gen interface standards (UCIe, PCIe, CXL, UALink, OIF-CEI, HBM) into package design rules and SI/PI methodology.Guide technical strategy for SI/PI at TIE, mentor engineers, and represent TIE in industry standards bodies, customer design reviews, and technical forums.
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