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ASIC Verification Engineer, Networking

Meta

Sunnyvale, CAJob$178–250K/yrSeen 6 days agoSeen in employer's feed 3 days ago

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At a glance

Compensation
$178–250K/yr
Location
Sunnyvale, CA
Work Authorization
Not specified

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Job overview

Meta is hiring an ASIC Design Verification Engineer in its Infrastructure organization to develop and verify IP and SoC designs for data center applications. The engineer will own verification closure for a design module or subsystem, using test planning, UVM-based testbench development, simulation, formal methods, and emulation. The role collaborates with software, hardware, design, emulation, and post-silicon teams to support first-pass silicon success.

Skills & qualifications

RequiredNice to have

Skills

ASIC VerificationSystemVerilog UVM/OVMC/C++ VerificationFunctional VerificationVerification InfrastructureVerification Cycle ExecutionPythonPerlTCLDebuggingEthernet400G MACNICRDMAPSPRoCECongestion ControlHigh-Speed Interface VerificationPCIeDDRHBMARM/RISC-v VerificationAutomated Verification FlowsData AnalysisPerformance Verification

Qualifications

Bachelor's in CS, Computer Engineering, or Equivalent8+ Years Verification Experience

Full job description

Summary:

Meta is hiring an ASIC Design Verification, Networking Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test planning, UVM-based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

Required Skills:

ASIC Verification Engineer, Networking Responsibilities:

  1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification

  2. Develop functional tests based on the verification test plan

  3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

  4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team

  5. Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals

  6. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools, and technologies from the industry

Minimum Qualifications:

Minimum Qualifications:

  1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

  2. Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience

  3. 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies and/or C/C++ based verification

  4. Experience in one or more of the following areas, along with functional verification - Ethernet, 400G MAC, NIC, RDMA, PSP, RoCE (RDMA over Converged Ethernet), congestion control, etc

  5. Experience in architecting and implementing design verification infrastructure, and in executing the full verification cycle

  6. Proficiency in scripting languages such as Python, Perl, or TCL to build tools and workflows for verification environments

  7. Experience in debugging and resolving complex verification challenges in IP or SoC designs

  8. Experience collaborating with cross-functional teams such as design, emulation, and silicon validation to drive verification milestones

Preferred Qualifications:

Preferred Qualifications:

  1. Experience with IP or integration verification of high-speed interfaces like Ethernet, PCIe, DDR, HBM

  2. Experience working across and building relationships with cross-functional design, model, and emulation teams

  3. Experience with the verification of ARM/RISC-V based sub-systems or SoCs

  4. Experience with the development of fully automated flows and scripts for data exploration, analysis, and performance verification

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].

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