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Wireless SOC Design Verification Engineer

Apple

Sunnyvale, CAJobSeen 2 days agoSeen in employer's feed 2 days ago

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At a glance

Compensation
No compensation found
Location
Sunnyvale, CA
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

Bachelor's degree

Job overview

Apple is hiring a Wireless SOC Verification Engineer to verify wireless-chip blocks and features, with scope growing toward subsystem and SOC integration. The engineer works across areas including power management, CPU subsystems, debug infrastructure, PCIe, bus fabric, boot sequencing, and peripherals. Verification is primarily simulation-based, with exposure to formal verification, UPF power-intent verification, and AI-assisted tools for test generation, debug, or verification closure.

Skills & qualifications

RequiredNice to have

Skills

SystemVerilogAnalytical ThinkingProblem SolvingUVMPCIeBus FabricNOCAHBAXIWiFi SOC VerificationBluetooth SOC VerificationFormal VerificationLow-Power DesignUPF IntegrationBoot-Up VerificationPower-Cycling VerificationHW/FW Interaction VerificationTeamworkCommunication

Qualifications

Bachelor's DegreeStrong Academic RecordGPA

Full job description

Role Number: 200690900-3956

Summary

Apple’s N1 wireless chip powers connectivity across every new iPhone — and its successor is already taking shape. As a Wireless SOC Verification Engineer, you’ll own your verification scope end-to-end — starting with a well-defined block or feature and growing in scope and complexity as you do. Over time, you’ll build depth in the IPs you know best and breadth across others, from block-level verification up toward subsystem and SOC integration.

Description

You’ll own verification for your scope — with a mentor’s guidance as you build toward full ownership — on a chip that ships in every new iPhone, starting with a block or feature sized to where you are and expanding from there. You’ll work across the Power Management Unit, the CPU subsystem, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, and peripherals like SPI and UART — primarily through simulation, with exposure to formal verification as you grow. Low-power is part of the picture too: you’ll get hands-on with power intent verification using UPF within your scope. AI is reshaping how the team works, and you’ll help apply AI-assisted tools for test generation, debug, or verification closure as part of your day-to-day.

Minimum Qualifications

  • Minimum requirement of a bachelors degree.

  • Strong academic record (GPA).

  • Proficiency in SystemVerilog.

  • Strong analytical thinking and problem-solving skills.

Preferred Qualifications

  • Familiarity with UVM methodology.

  • Exposure to PCIe, Bus Fabric, NOC, AHB, AXI-based bus architectures in a UVM environment.

  • Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC.

  • Experience with Formal Verification.

  • In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.

  • Should be a great teammate with excellent communication skills and the desire to seek diverse challenges.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.

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