Staff Engineer, Package Design

Position: Staff Engineer, Package Design Location: San Jose, CA

Job Id: 769

of Openings: 0

Staff Engineer, Package Design

Location: San Jose, CA (on-site)

Ayar Labs, the global leader in optical I/O chiplets, is harnessing silicon photonics to revolutionize the scaling of AI compute hardware. Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

Ayar Labs is pioneering the future of computing with our optical I/O technology, enabling dramatically higher bandwidth, lower latency, and improved power efficiency compared to traditional electrical interconnects. Our innovations in silicon photonics and advanced packaging are redefining system architectures for AI, HPC, cloud, and defense applications.

We are seeking a talented Senior Package Design Engineer to join our Platform Engineering team. This engineer will develop advanced package layouts for electro-optical ICs across flip-chip, 2.5D/3D, and heterogeneous integration packages, ensuring high performance, manufacturability, and reliability.

Essential Functions

• Manage package substrate layout design for flip-chip, 2.5D/3D, and heterogeneous integration packages, including interposer and chiplet-based architectures.
• Translate package design specifications into layout constraints and design rules for internal and external contract layout resources.
• Run design review meetings for substrate layout, and communicate regular design progress, risks, and schedule status to engineering and program management.
• Collaborate with internal stakeholders on signal integrity, power integrity, mechanical, thermal and physical design and collect simulation results for package sign off.
• Perform DRC, LVS, and ERC checks to ensure design quality and manufacturability.
• Collaborate with OSATs, foundries, and EDA vendors to drive design-for-manufacturability (DFM) and yield optimization.
• Maintain package design libraries, flows, and documentation.

Basic Qualifications

• B.S. in Electrical Engineering or related field plus 6+ years of experience in IC package layout and substrate design.
• Proficiency with Cadence Allegro Package Designer (APD).
• Solid understanding of high-speed interconnects (SerDes, Die-to-Die Interfaces), power delivery, and package-level signal integrity.
• Experience with substrate stack-up definition, routing constraints, and package reliability requirements.
• Strong problem-solving skills and ability to collaborate with a cross-functional, worldwide team across multiple time zones, including co-design with external vendor designers.

Preferred Qualifications

• M.S. in Electrical Engineering or related field plus 6+ years of experience in IC package layout and substrate design.
• Experience in heterogeneous integration, chiplet architectures, or silicon photonics packaging.
• Knowledge of thermal and mechanical reliability considerations in advanced packaging, including warpage analysis.
• Experience collaborating with OSATs and foundries on complex package substrates, from prototype through high-volume manufacturing (HVM).
• Experience with Cadence SKILL or similar design-automation scripting to streamline layout and constraint generation.
• Experience using agentic design and verification workflows (e.g., AI-assisted simulation setup, layout checking, or documentation generation).

Salary Range: $160,000 - $186,000

NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.

Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

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