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ASIC Design Verification Engineer

Meta

Menlo Park, CAJob$178–250K/yrSeen todaySeen in employer's feed today

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At a glance

Compensation
$178–250K/yr
Location
Menlo Park, CA
Work Authorization
Not specified

Olive lists jobs from US employers, including remote roles you can work from the United States.

Job overview

Meta is hiring an ASIC Design Verification Engineer in its Infrastructure organization to build IP and SoC solutions for data center applications. The engineer will own verification closure for a design module or subsystem, from test planning and UVM-based testbench development through closure, using simulation as well as formal methods and emulation. The role collaborates with software, hardware, design, emulation, and post-silicon teams to support first-pass silicon success.

Skills & qualifications

RequiredNice to have

Skills

ASIC VerificationSystemVerilog UVM/OVMC/C++ VerificationSoC VerificationEDA ToolsPythonTCLPerlShell ScriptingSV AssertionsFormal VerificationEmulationARM/RISC-v VerificationCross-Functional CollaborationMicro-Architectural Performance VerificationMercurial/Git/SVNVerification InfrastructureData-Center Design VerificationGPU/CPU VerificationUVM Environment Development

Qualifications

Bachelor's in CS or Related Field or Equivalent8+ Years Verification Experience

Full job description

Summary:

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

Required Skills:

ASIC Design Verification Engineer Responsibilities:

  1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification

  2. Develop functional tests based on verification test plan

  3. Drive Design Verification to closure based on defined verification metrics on the test plan, functional, and code coverage

  4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team

  5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals

  6. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications:

Minimum Qualifications:

  1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

  2. 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies and/or C/C++ based verification

  3. Experience in leading verification of SoC/chiplet or complex IP’s like PCIe, RoCE, DDR, HBM, Ethernet, Cache controllers, Network on Chip etc

  4. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Preferred Qualifications:

Preferred Qualifications:

  1. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation

  2. Experience with verification of ARM/RISC-V based sub-systems or SoCs

  3. Experience working across and building relationships with cross-functional design, model and emulation teams

  4. Experience with micro-architectural performance verification

  5. Experience with revision control systems like Mercurial(Hg), Git or SVN

  6. Track record of 'first-pass success' in ASIC development cycles

  7. Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

  8. Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs

  9. Experience verifying GPU/CPU designs

  10. Experience in development of UVM based verification environments from scratch

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].

How this job compares

Set against the 3,060 open Hardware Engineer jobs on Olive Jobs, counted November 6, 2026.

Pay
  • This posting$178–250K/yr
  • California median$145–214K/yr950 salary ranges
  • US median$132–204K/yr2,272 salary ranges

This range's midpoint, $214K, is 21% above the California median midpoint ($178K) — in the top quarter of Hardware Engineer salary ranges in California.

Openings
Olive Jobs lists 1,251 open Hardware Engineer jobs in California and 3,060 across the US. 1% of them nationwide are listed as remote or flexible.
Hiring the most in California
Experience
This posting asks for at least 8 years of experience; Hardware Engineer postings that state a minimum ask for 5 years at the median (2,588 postings).
Education
1,740 of the 3,060 open Hardware Engineer jobs (57%) ask for a bachelor's degree or higher.

Counted across the open, public US postings on Olive Jobs on November 6, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.

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