Intern, Architect - Link Architecture and Analysis
San Jose, CAInternshipPosted 5 days agoStill listed 3 days ago
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Job overview
Ayar Labs seeks a graduate or Ph.D. intern for its CTO architecture team in San Jose. The intern will work on EIC/PIC co-optimization and model architecture performance, collaborating with mixed-signal designers, photonics engineers, and system architects to evaluate NPO and CPO packaging paradigms against emerging OCI MSA specifications. The project will be tailored to the intern’s background and mentored by a senior link architect.
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Full job description
Position: Intern, Architect - Link Architecture and Analysis Location: San Jose, CA
Job Id: 748
of Openings: 0
Intern, Architect - Link Architecture and Analysis Term: May to August 2027
Please note:
- Position location is on-site in San Jose Office
- There is no immigration (except F1) or relocation support for this position
- Posting expires upon application threshold
Position Description
Ayar Labs, the global leader in optical I/O chiplets, is harnessing silicon photonics to revolutionize the scaling of AI compute hardware. Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
As the demand for AI compute scales, overcoming the I/O bottleneck requires continuous innovation in high-speed interconnects and silicon photonics. The CTO architecture team plays a critical role in defining the future of optical I/O by pioneering analyses of electro-optical boundaries, signal integrity, and the performance limits of next-generation interconnects.
We are looking for a motivated graduate or Ph.D. intern to join our team. In this role, you will work on EIC/PIC co-optimization and model the performance of architectures. You will have the opportunities to collaborate with mixed-signal designers, photonics engineers, and system architects to evaluate NPO and CPO packaging paradigms in alignment with emerging OCI MSA specifications.
This project will be tailored to your specific background and you will be mentored by a senior link architect.
Intern Skillset Needed
- Strong understanding of high-speed SerDes architecture, signal integrity, and optical link budget.
- Familiarity with advanced packaging architectures (CPO, NPO) and electro-optical transceiver components such as modulators, photodetectors, TIAs, and drivers.
- Strong programming and data analysis skills in Python or MATLAB.
- Knowledge of emerging high-speed I/O standards and scale-up fabrics (e.g., OCI MSA, IEEE 802.3 224G, ESUN, UALink) is a strong plus.
- Independent, highly motivated, and able to work collaboratively and autonomously, self-managing time effectively to take project tasks to completion.
Education Requirements
- Candidate should be actively pursuing a Ph.D. degree in Electrical Engineering or Optical Engineering
NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
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How this job compares
Set against the 383 open Architecture jobs on Olive Jobs, counted November 10, 2026.
- Pay
- This postingNot listed
- California median$150–245K/yr31 salary ranges
- Openings
- Olive Jobs lists 43 open Architecture jobs in California and 383 across the US. 3% of them nationwide are listed as remote or flexible.
- Experience
- Architecture postings that state a minimum ask for 8 years of experience at the median; the middle half ask for 5 to 10 years (280 postings).
- Education
- This posting asks for a doctorate or professional degree; 5 of the 383 open Architecture jobs (1%) ask for a doctorate or professional degree.
Counted across the open, public US postings on Olive Jobs on November 10, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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