DFT Lead
San Jose, CAJobSeen todaySeen in employer's feed today
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At a glance
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Job overview
The DFT Lead will implement hardware design-for-test features, develop DFT IP with multifunctional teams, and integrate testability features into full-chip designs. The role also contributes to reusable test and debug strategies for new silicon device models, including bare and stacked die. The project is expected to continue at least through September 2027.
Skills & qualifications
Skills
Qualifications
Full job description
Job Description
ASIC DFT experienced consulting engineers, lead-calibre. This project revision will at least go until September 2027.
Candidate Responsibilities:
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Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug
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Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
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Along with the DFT team, you will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
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The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
Skills and Requirements
1.Bachelor's or a Master's Degree in Electrical or Computer Engineering required, with at least 8-10 years of experience.
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Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and integrating 3rd party IP’s and high speed digital/analog macros
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Experience with ATPG and EDA tools like Tessent tool sets, Xcelium, Genus, Tempus/Primetime
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At least one project with hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to production Strong ability to establish/refine, train teams on DFT methodologies - from design phase to high volume production
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Ability to quickly learn new concepts and adapt to evolving technologies
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Excellent communication and presentation skills
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Strong attention to detail and system level understanding of networking and photonic solutions
We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to [email protected].
How this job compares
Set against the 1,104 open Hardware Engineering jobs on Olive Jobs, counted November 6, 2026.
- Pay
- This postingNot listed
- California median$172–245K/yr232 salary ranges
- California median$35–50/hr54 hourly ranges
- Openings
- Olive Jobs lists 366 open Hardware Engineering jobs in California and 1,104 across the US. Under 1% of them nationwide are listed as remote or flexible.
- Experience
- This posting asks for at least 8 years of experience; Hardware Engineering postings that state a minimum ask for 7 years at the median (690 postings).
- Education
- 362 of the 1,104 open Hardware Engineering jobs (33%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on November 6, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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