ASIC Engineering Intern, Formal Verification
Sunnyvale, CAInternship$6,660–12,014/moSeen 1 day agoSeen in employer's feed 1 day ago
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Job overview
Meta seeks an ASIC Engineering Intern, Formal Verification, to join its Infrastructure Silicon organization and work on accelerators for data center workloads. The intern will apply formal verification tools and methodologies to advanced IPs and subsystems, contributing to a scoped project alongside experienced ASIC engineers. The internship lasts 12 to 16 weeks and includes an intent to return to a degree program afterward.
Skills & qualifications
Skills
Qualifications
Full job description
Summary:
Meta is seeking an ASIC Engineer Intern, Formal Verification to join our Infrastructure Silicon organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. In this role, you will be an integral member of an ASIC team building accelerators for some of our top workloads, enabling our data centers to scale efficiently.You will have an opportunity to apply formal verification tools and methodologies to advanced IPs and sub-systems. Working alongside experienced ASIC engineers, you will contribute to formal verification planning, assertion development, formal testbench development and proof analysis on a scoped project of your own. You will learn to translate design intent into properties, analyze counterexamples and help establish the correctness of hardware designs. Come work and learn alongside our expert ASIC engineers to build "Green" data center accelerators.Internships are twelve (12) to sixteen (16) weeks long
Required Skills:
ASIC Engineering Intern, Formal Verification Responsibilities:
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Develop an understanding of the architecture, microarchitecture and intended behavior of the designs under verification.
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Contribute to formal verification plans by identifying design requirements, properties to prove and scenarios to cover.
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Write SystemVerilog Assertions (SVA), assumptions and cover properties to verify design functionality, protocol behavior and corner cases.
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Develop formal testbenches and harnesses, including clock, reset and environment models, with guidance from experienced engineers.
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Run formal verification tools, analyze proof results and debug counterexamples to distinguish design bugs from property or environment issues.
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Help improve proof convergence and assess formal coverage, including checking for vacuous assertions, unreachable scenarios and overly restrictive assumptions.
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Develop scripts to automate formal runs, regressions and results analysis, and collaborate with design and verification engineers to resolve issues and confirm fixes.
Minimum Qualifications:
Minimum Qualifications:
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Knowledge of computer architecture and digital logic design fundamentals, including sequential logic and finite-state machines
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Knowledge of a hardware description language such as Verilog, SystemVerilog or VHDL
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Familiarity with assertion-based verification or formal verification concepts, such as properties, assumptions and counterexamples
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Experience thinking critically and creatively about how to verify designs and solve problems
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Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
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Intent to return to a degree-program after the completion of the internship
Preferred Qualifications:
Preferred Qualifications:
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Coursework, academic projects or research involving formal methods, hardware verification or assertion-based verification
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Experience writing SystemVerilog Assertions or using formal property-checking tools such as Cadence JasperGold, Synopsys VC Formal or Siemens Questa Formal
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Experience with open-source formal verification tools and engines, such as SymbiYosys, ABC or Boolector
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Familiarity with bounded model checking, induction, safety and liveness properties, or techniques such as abstraction and assume-guarantee reasoning
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Scripting with Python, Tcl, Perl or Shell to automate verification tasks
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Experience using AI coding agents such as Claude Code or Codex to develop, debug or automate engineering workflows
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Exposure to data center application designs such as AI/ML accelerators, networking or video processing ASICs
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Familiarity with revision control systems such as Mercurial (Hg), Git or SVN
Public Compensation:
$6,660/month to $12,014/month + benefits
Industry: Internet
Equal Opportunity:
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].
How this job compares
Set against the 957 open Hardware Engineering jobs on Olive Jobs, counted November 5, 2026.
- Pay
- This posting$6,660–12,014/mo
- California median$172–245K/yr226 salary ranges
- California median$35–51/hr45 hourly ranges
- Openings
- Olive Jobs lists 348 open Hardware Engineering jobs in California and 957 across the US. Under 1% of them nationwide are listed as remote or flexible.
- Hiring the most in California
- Apple35 open
- Cisco25 open
- Anduril Industries22 open
- Experience
- Hardware Engineering postings that state a minimum ask for 7 years of experience at the median; the middle half ask for 5 to 10 years (614 postings).
- Education
- 345 of the 957 open Hardware Engineering jobs (36%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on November 5, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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