Design Verification Engineer - Accelerators
San Diego, CAJob$178–250K/yrSeen todaySeen in employer's feed today
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Job overview
Meta is hiring a Design Verification lead to own verification for complex computer vision and imaging accelerator IP and subsystems in custom silicon for AR glasses. The role defines verification strategy across multiple IPs and builds scalable DV infrastructure. It spans planning through coverage closure and sign-off, reusable testbench development, regression and coverage analytics, root-cause analysis, and methodology improvements.
Skills & qualifications
Skills
Qualifications
Full job description
Summary:
The AR glasses Meta is building run on custom silicon that delivers serious compute within a tight power budget. Our silicon team designs that silicon, with breakthrough work in computer vision, machine learning, imaging, and sensing. We're hiring a Design Verification (DV) lead to own verification for complex computer vision and imaging accelerator IP and subsystems. In this role, you'll define the verification strategy across multiple IPs and build DV infrastructure that scales across chips and programs.
Required Skills:
Design Verification Engineer - Accelerators Responsibilities:
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Shape architecture and microarchitecture decisions with architects, design, FW/SW, emulation, physical design and post-silicon teams so the chip is designed with verification in mind. Work with TPMs on schedules and sign-off criteria
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Own DV for multiple complex IPs or subsystems from start to finish, all the way from verification planning through coverage closure and sign-off
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Define the strategy across IPs, including the mix of simulation (constrained-random, UVM), formal, assertions, emulation and FPGA prototyping, plus power-aware verification (UPF)
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Design reusable testbench architectures, verification IP and libraries that are shared across IPs, subsystems and SoC generations
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Drive regression management, automated triage, coverage analytics, and compute-efficient runs (simulation and emulation) so the team can sustain high throughput as the number of designs grows
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Spot verification-quality and productivity gaps across the org, lead initiatives that measurably improve quality and time-to-closure, and drive DV methodology improvements, including AI-assisted ones
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Root-cause failures down to specific lines of RTL, reference model or FW/SW, and propose the fixes
Minimum Qualifications:
Minimum Qualifications:
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8+ years of hands-on verification experience with SystemVerilog, UVM and C/C++ at the IP, subsystem and SoC level
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Has led DV for complex IP or an SoC through tape-out, including owning sign-off
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Has defined and run verification plans, coverage strategies, and closure metrics (functional and code coverage) across multiple blocks or IPs
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Has built UVM verification environments from scratch and designed reusable verification components
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Deep experience in at least one of: formal verification, SystemVerilog Assertions (SVA), emulation/FPGA prototyping, or low-power (UPF) verification
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Strong scripting skills (Python, TCL, Perl, Shell) for building verification tools and flows
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Has led and mentored engineers and coordinated work across teams
Preferred Qualifications:
Preferred Qualifications:
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Has verified power-limited mobile, wearable or AR/VR System-on-Chips (SoCs)
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Has managed EDA vendors or contracted DV teams
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Has verified computer vision, imaging/ISP, DSP or ML accelerator designs
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Master's or PhD in EE/CE/CS
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Has rolled out methodology changes (formal, emulation, portable stimulus, ML/AI-assisted verification) across an org
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Has verified hardware against reference models written in C++ or Python, or co-simulated with firmware or software
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Has scaled DV infrastructure (regression farms, CI for hardware, coverage and triage dashboards) across multiple IPs or programs
Public Compensation:
$178,000/year to $250,000/year + bonus + equity + benefits
Industry: Internet
Equal Opportunity:
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].
How this job compares
Set against the 2,947 open Hardware Engineer jobs on Olive Jobs, counted November 4, 2026.
- Pay
- This posting$178–250K/yr
- California median$146–214K/yr901 salary ranges
- US median$132–204K/yr2,139 salary ranges
This range's midpoint, $214K, is 19% above the California median midpoint ($180K) — in the top quarter of Hardware Engineer salary ranges in California.
- Openings
- Olive Jobs lists 1,203 open Hardware Engineer jobs in California and 2,947 across the US. 1% of them nationwide are listed as remote or flexible.
- Experience
- This posting asks for at least 8 years of experience; Hardware Engineer postings that state a minimum ask for 5 years at the median (2,467 postings).
- Education
- 1,751 of the 2,947 open Hardware Engineer jobs (59%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on November 4, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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