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DFT Tech Lead

Retym, Inc

Austin, TXFull-timePosted 3mo agoStill listed 2 days ago

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At a glance

Compensation
No compensation found
Location
Austin, TX
Schedule
Full-time
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

Master's degree

Job overview

Retym, Inc is hiring a DFT Tech Lead. The DFT Tech Lead will define, implement, and deploy advanced design-for-test (DFT) methodologies for complex digital and mixed-signal chips. This role involves defining silicon test strategies, DFT/DFD architecture, and creating DFT and Debug specifications for next-generation SoCs, working closely with various design teams.

Key focus areas include Create SoC DFT strategy and architecture (ATPG/DFT/MBIST), Work on hierarchical design, and Debug all Design Rule checks, apply design fixes to achieve high test quality.

Successful candidates bring 8+ Years DFT Specification Experience, Silicon Bring‑Up Debug And Validation Experience, and Fault Modeling Experience. Important skills include DFT Specification Definition, DFT Architecture, DFT Insertion, DFT Analysis, Silicon Bring-Up, and Debug. Preferred (not required): IP Integration, Design Compiler, Fusion Compiler, and DFT Max.

Skills & qualifications

RequiredNice to have

Skills

DFT Specification DefinitionDFT ArchitectureDFT InsertionDFT AnalysisSilicon Bring-UpDebugValidation of DFT Features on ATEDebugging ATPG PatternsCompressed ATPG PatternsMBISTJTAG-Related IssuesFault ModelingIP IntegrationDesign CompilerFusion CompilerDFT MaxSpyGlassModusTessentTestKompressASIC DFTSynthesisSimulationVerification FlowAttention to DetailOrganizational SkillsProblem-Solving SkillsCommunication Skills

Qualifications

8+ Experience in DFTMaster's Degree in Electrical Engineering

Full job description

We are looking for a talented and experienced DFT Tech Lead.

As a DFT Tech Lead you will work closely with all other design teams – backend, vlsi, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies for highly complex digital and mixed-signal chips. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for complex next generation SoCs.

Requirements:

Minimum qualifications:

  • 8+ Experience in DFT specification definition, architecture, insertion, and analysis in designs
  • Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG-related issues
  • Experience in fault modeling

Preferred qualifications:

  • Master's degree in Electrical Engineering.
  • Experience in IP integration (memories, Test controllers, TAP, MBIST).
  • Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress.
  • Experience and understanding of ASIC DFT, synthesis, simulation and verification flow.
  • Excellent attention to detail organizational, problem-solving, and communication skills.

Responsibilities:

  • Create SoC DFT strategy and architecture (ATPG/DFT/MBIST)
  • Work on hierarchical design
  • Debug all Design Rule checks, apply design fixes to achieve high test quality
  • Insert all DFT logic - boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
  • Insert and hook up MBIST logic.
  • Define test plan for special analog IPs and implement.
  • Document DFT architecture and test sequences, including boot-up sequence associated with test pins.

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