Mixed Signal Verification Engineer
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At a glance
Job overview
Retym, Inc is hiring a Mixed Signal Verification Engineer. Retym, Inc. is seeking a Mixed Signal Verification Engineer to develop verification strategies for digital and analog designs using UVM methodologies. The role involves creating behavioral models for analog blocks, writing and debugging testbenches, and performing simulations of mixed-signal designs. The engineer will also troubleshoot unit-level, cluster-level, and top-level simulations.
Key focus areas include Develop verification strategies for digital and analog designs, Create behavioural models for analog blocks, and Write, execute, and debug testbenches.
Important skills include UVM Methodologies, Behavioural Models For Analog Blocks, Testbenches, Verilog, Behavioural Model Validation, and AMS Tools. Preferred (not required): Synopsys Tools, Cadence Tools, Verification Methodologies, and Simulators.
Skills & qualifications
Skills
Qualifications
Full job description
For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification engineer.
Requirements:
Key Responsibilities:
- Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications.
- Create behavioural models for analog blocks in accordance with guidelines provided by analog designers.
- Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks.
- Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models.
- Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs.
Minimum Qualifications
- 5+ years of experience
- Experience in Behavioural Modelling (BM) of Analog design for digital verification
- Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS]
- Experience in Verilog/SystemVerilog coding
- Experience in Virtuoso Schematics tools
- Basic knowledge in Analog design
Preferred Qualifications
- Experience in UVM
- Experience in both Synopsys and Cadence tools is an advantage
Additional Skills
- Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
- Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
- Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.
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