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At a glance
Requirements
Credentials this posting asks for.
Job overview
Mojo Vision is hiring an EDA Engineer. Mojo Vision, a Silicon Valley start-up, is developing a flexible micro‑LED platform for AI applications, including AI glasses and optical interconnects, using advanced 300 mm silicon architecture and GaN‑on‑Silicon emitters.
Key focus areas include Develop and maintain specialized software flows for analog, RTL, simulation, synthesis, place and route, and timing design stages, Evaluate and improve CAD methodologies, including AI‑driven automation and custom scripting, and Install, configure, and troubleshoot EDA tools from Cadence, Synopsys, and Siemens‑EDA.
Successful candidates bring BSEE Or MSEE and 10+ Years Of Experience In EDA. Important skills include Analog Flows, RTL, Simulation, Synthesis, Place And Route, and Timing. Preferred (not required): Leading Layout Team Members, Mentoring Layout Team Members, Strong Interpersonal Skills, and Problem Solving Skills.
Skills & qualifications
Skills
Qualifications
Full job description
EDA Engineer
Mojo Vision is a Silicon Valley start-up pioneering a highly flexible, wafers-in, wafers-out micro-LED platform to unlock AI applications in multiple market segments. Built over nine years by our skilled engineers, our system-level process combines advanced 300mm silicon architecture with GaN-on-Silicon emitters, proprietary quantum dots, and micro-lens arrays to resolve conventional trade-offs in size, brightness, bandwidth density, and power. Our scalable, manufacturing-ready approach enables breakthrough products such as AI glasses and next-generation optical interconnects for AI data centers. Mojo Vision is based in Cupertino, CA.
Roles and Responsibilities:
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Design Flow Development & Automation: Developing and maintaining specialized software flows for Analog flows, front-end (RTL, simulation), and back-end (synthesis, place and route, timing) design stages.
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CAD Methodology Improvement: Evaluating and enhancing design methodologies to increase efficiency, such as implementing AI-driven design automation or customizing scripts in SKILL, Python, Tcl, or Perl to streamline repetitive tasks.
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Tool Configuration and Support: Installing, configuring, and troubleshooting Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, or Siemens-EDA to ensure they meet project-specific requirements.
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Physical Verification & Sign-off: Managing design rule checks (DRC), layout vs. schematic (LVS) verification, and parasitic extraction to ensure the chip is manufacturable (tape-out ready).
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PDK and Library Management: Maintaining Process Design Kits (PDKs) and standard cell libraries provided by foundries to ensure accurate simulation and layout. Qualifications:
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BSEE or MSEE, and 10+ years of experience in EDA
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Tools: Expertise in major tools like Cadence, Synopsys (Virtuoso, Encounter, etc.).
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Scripting: Proficiency in SKILL, Python, Tcl, Perl for automation.
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Physical Design: Experience with DRC (Design Rule Check), LVS (Layout Versus Schematic), P&R (Place & Route), and related flows.
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Circuit Design: Understanding of digital and analog IC design principles.
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Semiconductor Process: Knowledge of fabrication processes and Device Physics.
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Programming: Familiarity with SKILL and hardware description languages (e.g., Verilog/VHDL) is often required.
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Experience in full-chip or block-level physical design.
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Developing/supporting PDKs (Process Design Kits) and PCELLs. Valuable Additional Qualifications:
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Experience with leading and mentoring layout team members Preferred Skills:
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Strong interpersonal and problem-solving skills
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Prior experience bringing communication products to mass production Salary Range: $188K-$230K
Level: Principal Engineer
To apply, email your resume to [email protected]
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