DFT Engineer

Retym, Inc

Austin, TXFull-timeNo compensation foundPosted 1mo agoVerified open 3 days ago

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At a glance

Compensation

No compensation found

Location

Austin, TX

Schedule

Full-time

Work Authorization

Not specified

Requirements

Credentials this posting asks for.

Master's degree

Job overview

Retym, Inc is hiring a DFT Engineer. The DFT Engineer will define, implement, and deploy advanced design-for-test (DFT) methodologies for complex digital and mixed-signal chips. This role involves working closely with backend, verification, and analog design teams, focusing on silicon test strategies, DFT/DFD, and BIST for next-generation SoCs.

Key focus areas include Implement SoC DFT strategy and architecture (ATPG/DFT/MBIST), Work on hierarchical design, and Debug all Design Rule checks, apply design fixes to achieve high test quality.

Successful candidates bring 5+ Years DFT Experience. Important skills include DFT Specification Definition, DFT Architecture, DFT Insertion, DFT Analysis, Silicon Bring-up, and Debug. Preferred (not required): IP Integration, Design Compiler, Fusion Compiler, and DFT Max.

Skills & qualifications

RequiredNice to have

Skills

DFT Specification DefinitionDFT ArchitectureDFT InsertionDFT AnalysisSilicon Bring-UpDebugValidation of DFT Features on ATEDebugging ATPG PatternsCompressed ATPG PatternsMBISTJTAG-Related IssuesFault ModelingIP IntegrationDesign CompilerFusion CompilerDFT MaxSpyGlassModusTessentTestKompressASIC DFTSynthesisSimulationVerification FlowAttention to DetailOrganizational SkillsProblem-Solving SkillsCommunication Skills

Qualifications

5+ Experience in DFTMaster's Degree in Electrical Engineering

Full job description

For an exciting well funded start-up we are looking for a DFT Engineer.

As a DFT Engineer you will work closely with all other design teams – backend, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies for highly complex digital and mixed-signal chips. You will work on silicon test strategies, DFT/DFD, BIST for complex next generation SoCs.

Requirements:

Minimum qualifications:

5+ Experience in DFT specification definition, architecture, insertion, and analysis in designs
Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG-related issues
Experience in fault modeling

Preferred qualifications:

Master's degree in Electrical Engineering.
Experience in IP integration (memories, Test controllers, TAP, MBIST).
Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress.
Experience and understanding of ASIC DFT, synthesis, simulation and verification flow.
Excellent attention to detail organizational, problem-solving, and communication skills.

Responsibilities:

Implement SoC DFT strategy and architecture (ATPG/DFT/MBIST)
Work on hierarchical design
Debug all Design Rule checks, apply design fixes to achieve high test quality
Insert all DFT logic - boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic.
Work on test plan for special analog IPs and implement.
Document DFT working processes.

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