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Mid Level ASIC Design Engineer

Tensordyne

Sunnyvale, CAJobNo compensation foundPosted 3w agoVerified open 6 days ago
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At a glance

Compensation
No compensation found
Location
Sunnyvale, CA
Work Authorization
Not specified

Job overview

Tensordyne is hiring a Mid Level ASIC Design Engineer. Tensordyne seeks a Mid Level Hardware Design Engineer to own hardware system development, including schematics, PCB layout, mechanical design, component selection, and testing. The role collaborates across ASIC, software, product, and operations teams to develop industry‑leading AI inference hardware products.

Key focus areas include Author/Understand micro-architecture specifications and participate in specification and test plan reviews, Implement complex RTL designs, and Integrate CPU and other relevant IPs into the CPU sub-system.

Successful candidates bring 3+ Years ASIC Design Experience, B.S. In Electrical Engineering, and B.S. In Computer Engineering. Important skills include Verilog, ARM Architecture, MIPS Architecture, Memory Hierarchy, Virtual Memory, and Transformers (Electrical). Preferred (not required): AI Architectures For Convolution, AI Architectures For Transformer, AI Architecture Exploration, and Convolution Workloads.

Skills & qualifications

RequiredNice to have

Skills

VerilogARM ArchitectureMIPS ArchitectureMemory HierarchyVirtual MemoryTransformers (Electrical)Verilog RTL Implementation3rd-Party IP Block Selection3rd-Party IP Block IntegrationFrontend SynthesisPlace-and-Route GuidanceTiming ClosureMicro-Architecture SpecificationRTL DesignsCPU IP Integration Into SoCPhysical Design CollaborationPower OptimizationCode Coverage AnalysisDiagnostic TestingPost-Silicon ValidationSoftware Bring-UpRTL Logic DesignSystem VerilogARM ArchitecturesRISC-v ArchitecturesMIPS ArchitecturesCache CoherencyMulticore CPU OperationAMBA ProtocolAPB ProtocolAXI ProtocolSPIeMMCMIIGPIOI2CASIC Development ProcessFront-End ToolsFront-End MethodologiesLow Power DesignUPF FlowSelf-StarterHighly-MotivatedAI Architectures for ConvolutionAI Architectures for TransformerASIC DesignRTL DesignIP IntegrationRISC-v ArchitectureSPI InterfaceeMMC InterfaceMII InterfaceGPIO InterfaceI2C InterfaceAI Architecture ExplorationConvolution WorkloadsTransformer WorkloadsAI ArchitectureMicroarchitecture SpecificationRTL ImplementationFront-End SynthesisMicroarchitecture DesignVerification CollaborationSynthesisAI ArchitecturesTiming AnalysisVerificationDynamic Start-Up EnvironmentCPU IP IntegrationFront-End ASIC ToolsConvolutional Neural Network Accelerator DesignTransformer Workload KnowledgeCPU IPSOCSpecification ReviewTest Plan ReviewMemory Hierarchy KnowledgeCache Coherency KnowledgeVirtual Memory KnowledgeMulticore CPU Operation KnowledgeARMRISC-VMIPSAMBAAPBAXIASIC Design ProcessSelf-Starter AttitudeConvolutionTransformerMicroarchitectureASIC Microarchitecture DesignConvolutional Neural Network AcceleratorFront‑End Design Tools3rd-Party IP Blocks IntegrationMicro-Architecture SpecificationsPhysical Design Team CollaborationDiagnostic and Post-Silicon Validation TestsFront-End Tools and MethodologiesCollaborationDiagnostic and Post‑Silicon ValidationDiagnostic ValidationTiming Closure at High Frequencies

Qualifications

3+ Years ASIC Design ExperienceB.S. Degree in Electrical or Computer EngineeringM.S. Degree Preferred

Full job description

About Tensordyne

Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Tensordyne is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment.

About the role:

To keep pace in this exciting, multi-disciplinary field, we’re looking for a Mid Level Hardware Design Engineer. You will be in a unique position to have ownership of a wide-ranging list of hardware system development aspects, including schematics, PCB layout and mechanical design, component selection and collaborating with operations in AVL management, EVT/DVT/PVT testing and certification. You will also have an opportunity to make an impact on design and bringup of development systems, reference platforms and volume products.

This hands-on multi-disciplinary role provides a unique opportunity to interact directly with ASIC, software, product and operations teams to gather necessary requirements and specifications, and develop industry-leading AI Inference HW products.

Responsibilities:

  • Author/Understand micro-architecture specifications and participate in specification and test plan reviews.

  • Implement complex RTL designs.

  • Integrate CPU and other relevant IPs into the CPU sub-system.

  • Collaborate with the physical design team to resolve implementation and timing issues and to optimize power.

  • Analyze code coverage and provide feedback to the verification team to achieve coverage closure.

  • Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab. Required Qualifications:

  • 3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.

  • Experience in IP integration, specifically CPU IP into SoC.

  • Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation

  • Familiarity with AMBA/APB/AXI Protocol

  • Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ....

  • Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies.

  • Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains

  • Previous experience with timing closure at high frequencies is a plus.

  • Interest to explore AI architectures for convolution, transformer and other kinds of workloads

  • Self-starter and highly-motivated to work in a dynamic start-up environment.

  • B.S. (M.S. preferred) degree in Electrical or Computer engineering.

Tensordyne's culture was built on the following values that are equally important to us as business:

  • Put people first. We only succeed when our people succeed.
  • Ethics and integrity always; Being open, honest, and respectful of everyone.
  • Think Big. Be ambitious and have audacious goals.
  • Aim for excellence. Quality and excellence count in everything we do.
  • Own it and get it done. Results matter!
  • Make Each Person Better together than they would be as an individual.
  • Embrace each others’ differences.
  • Embrace that there will be differences.

Tensordyne is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.

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Mid Level ASIC Design Engineer at Tensordyne | Olive Jobs