
Analog Mixed Signal SerDes Design Engineer
Cupertino, CAFull-timeSeen todaySeen in employer's feed today
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Job overview
Apple seeks an Analog Mixed-Signal Design Engineer for its high-speed SerDes team, developing high-performance wireline transceiver IP for system-on-chip products. The role covers circuit topology evaluation, block specifications, transistor-level implementation, behavioral modeling, mask design, and IP delivery. The engineer collaborates with cross-functional and SoC teams and communicates progress and technical insights. Preferred qualifications include high-speed serial-link experience and expertise across analog, mixed-signal, and digital design.
Skills & qualifications
Skills
Qualifications
Full job description
Weekly Hours: 40
Role Number: 200693686-0836
Summary
We are seeking skilled Analog Mixed-Signal designers to join our high-speed SerDes team! Our team specializes in building next generation high-performance wireline transceivers delivering intellectual-property (IP) for Apple’s world-leading system-on-chip (SOC). In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to create state-of-the-art IPs key to Apple’s products. You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn end-to-end system while exceeding the highest expectations of quality, innovation and efficiency. If you have strong fundamentals and a track record of tackling technical challenges, If you are passionate about learning new skills and improving the value of your work, If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems, We invite you to join and grow with our team!
Description
We work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO) with best-in-class power, performance, and area (PPA). We work with cross-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create block-level specifications, and execute on transistor-level implementation and behavioral modeling. We drive mask design to implement layout view of designs. We closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs, on regular basis we interact with peers/management to communicate progress and discuss new insights making it a lively and interactive work environment.
Minimum Qualifications
- Bachelors/Masters in Electrical Engineering
Preferred Qualifications
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The ideal candidate should have deep understanding of AMS design with experience in high-speed serial links.
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Proven understanding and experience of designing analog mixed-signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
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Solid understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
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Good grasp and understanding of digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)
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Experience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with the understanding of digital design concepts
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Knowledge of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 20+ Gbps NRZ and PAM applications
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Knowledge of CDR architectures and implementations
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Knowledge of lab equipments and testing
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Experience in AMS circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)
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Hands-on experience in advanced CMOS technologies, design with FinFet technology
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Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
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Experience in the following areas is a plus
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Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
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Experience in lab testing of high-speed serial I/O, debug and data analysis techniques
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Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY)
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Skills in scripting and automation to improve efficiency
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
How this job compares
Set against the 2,925 open Electrical Engineering jobs on Olive Jobs, counted November 6, 2026.
- Pay
- This postingNot listed
- California median$145–205K/yr224 salary ranges
- California median$33–42/hr55 hourly ranges
- Openings
- Olive Jobs lists 344 open Electrical Engineering jobs in California and 2,925 across the US. 3% of them nationwide are listed as remote or flexible.
- Experience
- Electrical Engineering postings that state a minimum ask for 6 years of experience at the median; the middle half ask for 5 to 10 years (1,904 postings).
- Education
- 1,363 of the 2,925 open Electrical Engineering jobs (47%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on November 6, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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