
Wireless SoC Design Engineer
Irvine, CAJobSeen 1w agoSeen in employer's feed 4 days ago
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At a glance
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Requirements
Credentials this posting asks for.
Job overview
The Wireless SoC Design Engineer will design CPU-based subsystems for high-performance, low-power wireless SoCs. The role works with SoC architects, IP developers, and software, firmware, and platform engineering teams to meet power, performance, and area goals. Responsibilities include hardware/software/power partitioning and integrating standard and custom hardware IPs into SoCs as part of Apple’s wireless silicon development efforts.
Skills & qualifications
Skills
Qualifications
Full job description
Role Number: 200688941-1697
Summary
Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.
Description
In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. As a member of the team, you will work closely with SoC architects and IP developers to develop SoCs that meet the power, performance, and area goals for Apple devices, with a particular focus on low power metrics. You will engage in hardware/software/power partitioning discussions alongside software, firmware, and platform engineering teams. You will integrate industry standard and custom hardware IPs into SoCs. This is a highly visible role, where you will be at the center of the ASIC design efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.
Minimum Qualifications
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Minimum requirement of a bachelors degree.
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Familiarity with the ASIC design flow.
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Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
Preferred Qualifications
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MSEE with some years of industry experience
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Shown experience writing micro-architecture specifications and converting them to design
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Exposure to design methodologies and industry standard EDA tools.
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Experience with AXI/AHB bus fabric and processor sub-systems.
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Understanding of UPF and low-power design & implementation techniques.
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Self-starter and willingness to learn.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
How this job compares
Set against the 2,947 open Hardware Engineer jobs on Olive Jobs, counted October 29, 2026.
- Pay
- This postingNot listed
- California median$146–214K/yr906 salary ranges
- California median$53–65/hr25 hourly ranges
- Openings
- Olive Jobs lists 1,197 open Hardware Engineer jobs in California and 2,947 across the US. 1% of them nationwide are listed as remote or flexible.
- Experience
- Hardware Engineer postings that state a minimum ask for 5 years of experience at the median; the middle half ask for 3 to 8 years (2,476 postings).
- Education
- This posting asks for a bachelor's degree; 1,840 of the 2,947 open Hardware Engineer jobs (62%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on October 29, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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