
ASIC DFT Engineer
San Jose, CAFull-time$122–195K/yrSeen todaySeen in employer's feed today
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Job overview
Broadcom’s ASIC Product Division seeks a DFT Engineer for its San Jose Development Center. The engineer will participate in SoC DFT implementation, verification, and debug, including post-silicon bring-up. The role supports test insertion, pattern generation, coverage improvement, and silicon debug, and collaborates with physical design, STA, test engineering, manufacturing, and customer teams.
Skills & qualifications
Skills
Qualifications
Benefits
Full job description
USA-CA San Jose Innovation Drive
Full time
R027650
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Job Description:
ASIC DFT Engineer
Broadcom's ASIC Product Division is seeking candidates for a DFT Engineer position at our San Jose, California Development Center. The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up.
The candidate will support various phases of SoC DFT-related activities for Broadcom APD’s designs, including test insertion, pattern generation, coverage improvement, and basic silicon debug. The role involves collaborating with cross-functional teams, including Physical Design and STA engineers.
Basic coding/scripting skills in TCL, Perl, Python, C++, or Verilog are expected.
Responsibilities:
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Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
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Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
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Working closely with STA and DI Engineers design closure for test
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Generating, Verifying & Debugging Test vectors before tape release.
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Validating & Debugging Test vectors on ATE during the silicon bring up phase
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Assisting with silicon failure analysis, diagnostics & yield improvement efforts
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Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
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Working closely with I/P DFT engineers & other stakeholders
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Debugging customer returned parts on the ATE
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Innovating newer DFT solutions to solve testability problems in 3nm & beyond
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Automating DFT & Test Vector Generation flows
Skills/Experience:
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Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
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Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
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Logic BIST design and debug experience
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Well-versed in ATPG vector generation, simulation, debug. (TetraMax, Fastscan)
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Experience in Verilog coding, testbench generation & simulation
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Memory BIST insertion and verification experience (SRAM, CAM, eDRAM)
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The ability to work in a multi-disciplined, cross-department environmentSolid knowledge in analog and digital circuit design, and device physics fundamentalsGood understanding of Si processing, logical and physical synthesis, and transistor reliability principles
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Excellent problem solving, debug , root cause analysis and communication skills
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Experience working on ATE is a plus
Education & Experience:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 10+ years of experience.
Compensation and Benefits
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Welcome! Thank you for your interest in Broadcom!
We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.
For more information please visit our video library (http://www.broadcom.com/videos) and check out our Connected by Broadcom (https://www.broadcom.com/support/resources/video-webinar-library?channel=5c9658f7c1d34eca91c6cc16178e5b1b&video=7d72b04ea50046a394e682fab640ce20) series.
Follow us on Linked In Broadcom Inc (https://www.linkedin.com/company/broadcom) .
How this job compares
Set against the 2,907 open Hardware Engineer jobs on Olive Jobs, counted November 11, 2026.
- Pay
- This posting$122–195K/yr
- California median$145–215K/yr952 salary ranges
- US median$133–202K/yr2,182 salary ranges
This range's midpoint, $158K, is 12% below the California median midpoint ($179K) — in the middle half of Hardware Engineer salary ranges in California.
- Openings
- Olive Jobs lists 1,226 open Hardware Engineer jobs in California and 2,907 across the US. 1% of them nationwide are listed as remote or flexible.
- Experience
- This posting asks for at least 10 years of experience — more than three in four Hardware Engineer postings that state a minimum ask for (median 5 years, across 2,400 postings).
- Education
- 1,578 of the 2,907 open Hardware Engineer jobs (54%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on November 11, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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