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Staff/ Sr. Staff Design Verification Engineer - QGOV

Qualcomm Incorporate

Boulder, COFull-time$148–246K/yrSeen 3w agoSeen in employer's feed 2 days ago

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At a glance

Compensation
$148–246K/yr
Location
Boulder, CO
Schedule
Full-time
Work Authorization
US work authorization required

Olive lists jobs from US employers, including remote roles you can work from the United States.

Requirements

Credentials this posting asks for.

Security clearance, required

Job overview

Qualcomm seeks a Design Verification Engineer to verify hardware building blocks, design macros, and standard interfaces. The role covers verification planning and execution, testbench development, simulation and emulation, coverage, and debugging. The posting states the role must be performed in San Diego five days a week and requires U.S. citizenship and eligibility for a government security clearance.

Skills & qualifications

RequiredNice to have

Skills

RTL Design, requiredFPGA Design, requiredEmbedded Systems, requiredDesign Verification, requiredEmulation, requiredDebugging, requiredCommunication Protocols, nice to haveSystemVerilog, nice to haveUVM, nice to haveAssertion-Based Verification, nice to haveCoverage-Based Verification, nice to haveChip-Level Functional Modeling, nice to haveObject-Oriented Programming, nice to haveSystemC, nice to haveBehavioral Modeling, nice to haveStructural Modeling, nice to haveSimulation, nice to haveMake-Based Build Flows, nice to haveVivado, nice to haveGit, nice to haveGerrit, nice to haveFormal Verification, nice to haveStatic Verification, nice to havePalladium, nice to haveZebu, nice to haveVeloce, nice to haveDesign Synthesis, nice to haveDesign Optimization, nice to haveC/C++ DPI, nice to haveJTAG, nice to haveLab Test Equipment, nice to haveGLS, nice to havePerl, nice to havePython, nice to haveLinux, nice to haveInitiative, nice to haveDiscipline, nice to haveMotivation, nice to haveQuality Focus, nice to haveTeamwork, nice to have

Qualifications

5+ Years RTL/FPGA Experience, required5+ Years Design Verification Experience, requiredU.S. Citizenship, requiredSecurity Clearance Eligibility, requiredBachelor's in Science, Engineering, or Related Field + 6+ Years ASIC Experience or Master's in Science, Engineering, or Related Field + 5+ Years ASIC Experience or PhD in Science, Engineering, or Related Field + 4+ Years ASIC Experience, required

Full job description

General Summary: Design Verification Role: - Familiarity with RTL design in Verilog and System Verilog - Develop verification methodology, ensuring scalable and portable environment across simulation and emulation. - Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc) . - Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals - Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches - Develop verification methodology, ensuring scalable and portable environment across simulation and emulation. - Develop and maintain emulation environment to collect metrics related to emulation environment. **Need to be in San Diego full time, 5 days a week Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. **** Must be a U.S. citizen and eligible to receive a U.S. Government security clearance **** Required Qualifications: - 5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture - 5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows Relevant experience of 5+ yrs in any of the mentioned domain - Design/Verification/ Implementation Preferred Qualifications: One or more of the following preferred: - Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc. - Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology - Good understanding of chip-level functional model building - Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C - Knowledge of Behavioral and Structural models and familiarity with simulation environments - Experience customizing and debugging make-based build flows and working with Xilinx's Vivado tools - Experience with cm tools such as Git and Gerrit. - Experience in formal / static verification methodologies will be a plus - Experience with emulation platforms -- Palladium, Zebu, Veloce, FPGAs. - Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog. - Experience with C/C++ DPI transactors and monitors. - Develop and maintain emulation environment to collect metrics related to emulation environment. - Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors. - Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations. - Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. - Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc. - Experience with GLS, and scripting languages such as Perl, Python is a plus - Linux OS proficiency The ideal candidate would be a self-starter with strong initiative, discipline, motivation, and a focus on quality. The candidate must be a team player and be flexible and open to a variety of task assignments within the team. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verificati n, validation, integration, or related work experience. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected]{rel="noopener noreferrer" target="_blank"} or call Qualcomm's toll-free number found here{rel="noopener noreferrer" target="_blank"}. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $147,600.00 - $246,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer -- and you can review more details about our US benefits at this link{rel="noopener noreferrer" target="_blank"}. If you would like more information about this role, please contact Qualcomm Careers{rel="noopener noreferrer" target="_blank"}.

How this job compares

Set against the 2,907 open Hardware Engineer jobs on Olive Jobs, counted November 11, 2026.

Pay
  • This posting$148–246K/yr
  • Colorado median$121–178K/yr117 salary ranges
  • US median$133–202K/yr2,182 salary ranges

This range's midpoint, $197K, is 31% above the Colorado median midpoint ($151K) — in the top quarter of Hardware Engineer salary ranges in Colorado.

Openings
Olive Jobs lists 131 open Hardware Engineer jobs in Colorado and 2,907 across the US. 1% of them nationwide are listed as remote or flexible.
Hiring the most in Colorado
Experience
This posting asks for at least 4 years of experience; Hardware Engineer postings that state a minimum ask for 5 years at the median (2,400 postings).
Education
1,578 of the 2,907 open Hardware Engineer jobs (54%) ask for a bachelor's degree or higher.

Counted across the open, public US postings on Olive Jobs on November 11, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.

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