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Design Engineer I - II or Senior Design Engineer, Texas Institute for Electronics

UNIVERSITY OF TEXAS AT AUSTIN

AUSTIN, TXJobSeen 6 days agoSeen in employer's feed 6 days ago

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At a glance

Compensation
No compensation found
Location
AUSTIN, TX
Work Authorization
Not specified

Olive lists jobs from US employers, including remote roles you can work from the United States.

Job overview

The Design Engineer will develop mixed-signal circuits, test vehicles, workflows, modeling methods, and standard cells for the Texas Institute for Electronics’ 3D Assembly Design Kit. The role works with product and test engineering teams, EDA vendors, and internal and external design teams to evaluate and improve semiconductor packaging designs, models, and workflows. It also supports industry collaboration and advances packaging performance, reliability, manufacturability, and testability.

Skills & qualifications

RequiredNice to have

Skills

Mixed-Signal Circuit Design2.5D/3D ModelingStandard Cell DesignBIST MethodologiesEDA ToolsSemiconductor Packaging ModelingPythonC++MATLABCircuit AutomationLayout AutomationDesign StandardsPackaging Experiments3DHI ModelingMultiphysics ModelingSignal IntegrityRFAnalog/Digital Performance

Full job description

Design and develop mixed signal circuits, test vehicles, and test?structures to support the development of TIE's 3D-ADK (Assembly Design Kit)Help develop workflows, 2.5D/3D modeling methods, and standard cells to comprehend and optimize Power/Thermal/Mechanical/Signal Integrity/RF impacts of multi-chiplet, heterogeneous micro-systems.Work with Product and Test engineering teams to comprehend and design in requirements to ensure performance, yield, reliability, and support BIST (Built in Self-Test) methodologies.Collaborate closely with EDA vendors and their tool/modeling solutions to evaluate effectiveness and drive improvements in their tool offerings and capability. Develop and implement advanced models to analyze and predict the effects of semiconductor packaging on device performance, reliability, and lifetimes.Improve automation of circuits and layouts to support standard cells and structures using Python, C+/+, MATLAB or other scripting languages.Participate in industry design standards workshops and consortiums to promote an open access 3DHI manufacturing chiplet eco-system. Bring key aspects back into TIE designs and workflows to ensure we are compatible with industry trends.Collaborate with internal and external design teams to ensure package compatibility with semiconductor die and system-level requirements.Design and execute experiments to evaluate and optimize packaging performance, reliability, and manufacturability.Conduct rigorous simulation and 3DHI modeling studies to verify the performance, reliability, and testability of semiconductor packaging designs. (multi-physics modeling includes: Power, Thermal, Mechanical, Signal Integrity, RF, Analog/Digital performance)Stay current with industry trends and emerging technologies in semiconductor packaging and design integration to drive innovation and continuous improvement.

How this job compares

Set against the 2,837 open Design Engineer jobs on Olive Jobs, counted October 27, 2026.

Pay
  • This postingNot listed
  • Texas median$117–160K/yr132 salary ranges
  • US median$41–55/hr93 hourly ranges
Openings
Olive Jobs lists 318 open Design Engineer jobs in Texas and 2,837 across the US. 3% of them nationwide are listed as remote or flexible.
Hiring the most in Texas
Experience
Design Engineer postings that state a minimum ask for 5 years of experience at the median; the middle half ask for 3 to 7 years (2,305 postings).
Education
2,086 of the 2,837 open Design Engineer jobs (74%) ask for a bachelor's degree or higher.

Counted across the open, public US postings on Olive Jobs on October 27, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.

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