
Design Engineering Architect – Systems and Interfaces
Austin, TXFull-time$186–345K/yrSeen 2 days agoSeen in employer's feed 2 days ago
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Job overview
Cadence seeks a senior technical leader to enable integration and adoption of its interface IP in complex customer SoCs. The architect works with sales, marketing, development engineering, and customer support on product definition and pre- and post-sales engagements. The role also develops technical content and examples, supports customer integration challenges, and provides guidance on system-level IP deployment.
Skills & qualifications
Skills
Qualifications
Benefits
Full job description
SAN JOSE
AUSTIN
Full time
R57024
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design Engineering Architect – Systems and Interfaces
San Jose
Job Description:
The SSG Central Applications Engineering team seeks an experienced SoC design engineer to enable the integration and deployment of Cadence IP in complex customer system designs. As a Design Engineering Architect, you will serve as a senior technical leader, enabling the successful integration and adoption of Cadence interface IP in our customers’ SoCs.
In this role, you will work closely with the SSG IP sales, marketing, development engineering, and customer support teams. You will contribute to product definition, develop technical content and examples, and drive complex pre-sales and post-sales engagements.
The Cadence Silicon Solutions Group (SSG) develops and licenses IP for SoC and ASIC designs, including high-performance DSPs, CPUs, interface IP, DDR controllers, hardware accelerators, and subsystems. These technologies enable applications such as machine learning, edge AI, radar, audio, speech, and vision. Leading semiconductor companies use Cadence IP in billions of chips shipped annually. This role enables customer adoption of Cadence IP and addresses complex system integration challenges.
Responsibilities:
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Serve as the technical authority for Cadence interface controllers and system-level IP integration in customer engagements.
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Lead resolution of critical customer issues and escalations, coordinating with development engineering, sales, marketing, and customer support teams on pre-sales and post-sales engagements.
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Develop reference designs, technical collateral, and application notes for IP integration, SoC design, and verification.
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Develop and deliver training for customers and field application engineers.
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Provide advanced technical guidance to customers, support teams, and field application engineers on IP integration, configuration, and system-level deployment.
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Lead product evaluations and release-readiness reviews, identifying integration risks, usability gaps, and advanced customer use cases.
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Analyze and propose enhancements to our products and documentation based on customer needs and use cases.
Required Skills:
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Demonstrated expertise in the RTL design, verification, and debug of high-speed interface protocols such as PCIe, UCIe, and Ethernet.
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Experience integrating IP into complex SoCs, with a strong understanding of system architecture, interfaces, and on-chip interconnects.
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Experience with AMBA protocols, including ACE, CHI, AXI, and APB.• Proficient in writing and debugging RTL (Verilog, SystemVerilog).
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Experience with end-to-end SoC implementation flows, including RTL synthesis, design constraints, DFT, CDC, and static timing analysis.
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Demonstrated ability to analyze complex hardware and system problems, identify root causes, and drive cross-functional teams to resolution.
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Strong written and verbal communication skills.
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A BS in EE/CS with 12+ years, or an MS in EE/CS with 8+ years of relevant work experience.
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Ability to travel up to 10% of the time, including internationally.
The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl\_jobs)
Equal Employment Opportunity Policy:
Cadence is committed to equal employment opportunity throughout all levels of the organization.
- Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/equal-employment-opportunity-policy.pdf)
We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [email protected].
Privacy Policy:
Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en\_US/home/privacy/privacy-policy.html) .
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E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/e-verify-participation-poster.pdf)
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
How this job compares
Set against the 418 open Applications Engineer jobs on Olive Jobs, counted November 7, 2026.
- Pay
- This posting$186–345K/yr
- Texas median$101–158K/yr21 salary ranges
- US median$101–150K/yr235 salary ranges
This range's midpoint, $265K, is 101% above the Texas median midpoint ($132K) — in the top quarter of Applications Engineer salary ranges in Texas.
- Openings
- Olive Jobs lists 61 open Applications Engineer jobs in Texas and 418 across the US. 6% of them nationwide are listed as remote or flexible.
- Hiring the most in Texas
- Texas Instruments17 open
- Emerson5 open
- QORVO TEXAS LLC5 open
- Experience
- This posting asks for at least 8 years of experience — more than three in four Applications Engineer postings that state a minimum ask for (median 5 years, across 299 postings).
- Education
- 200 of the 418 open Applications Engineer jobs (48%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on November 7, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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