
Wireless PHY Systems Engineer — Pre-Silicon Emulation
San Francisco, CAJobSeen 2w agoSeen in employer's feed 5 days ago
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Job overview
Apple seeks a wireless PHY systems engineer to own the pre-silicon emulation environment for wireless SoCs, bringing up new builds and enabling early design verification. The role spans digital design, firmware, and validation, with responsibility for evolving emulation infrastructure across silicon generations and contributing to Bluetooth and UWB emulation and lab bring-up. Palladium experience is not required; Apple will help the right candidate ramp up.
Skills & qualifications
Skills
Qualifications
Full job description
Role Number: 200689125-3401
Summary
Come join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this role, you will help de-risk our silicon well ahead of tape-out by owning the pre-silicon emulation environment that enables the team to exercise and verify new designs early and with confidence. We are looking for a wireless PHY systems engineer for this role: your understanding of the full signal chain, from RF and PHY through MAC and firmware, will help ensure that each emulated design not only comes up but behaves as intended. Prior Palladium experience is not required, and we will help the right candidate ramp up on the platform. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.
Description
This role is central to Apple's pre-silicon verification effort for wireless SoCs, centered on the Palladium emulation platform. You will be the first to bring up each newly released emulation build, and you will design and own the framework and infrastructure — register maps, initialization and boot sequences, clock and reset, and system-level configuration — that brings the emulated SoC into an operational state and enables the wider team to run their own design verification. Working at the intersection of digital design, firmware, and validation, you will own and evolve this infrastructure across successive silicon generations, while also contributing to pre-silicon emulation and lab bring-up of Bluetooth and UWB silicon.
Minimum Qualifications
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Bachelor's degree with 10 years of relevant experience.
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Solid foundation in Digital Signal Processing (DSP) and wireless communications, with working knowledge of PHY and MAC layer concepts.
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Hands-on software programming skills for system modeling, simulation, and test, with proficiency in MATLAB and C/C++.
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Familiarity with analog/RF impairments common in wireless systems (e.g., phase noise, IQ imbalance, nonlinearity).
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Experience with or knowledge of wireless standards such as Bluetooth, Ultra-Wideband (UWB), or other wireless protocols.
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Experience collecting, processing, and visualizing large-scale simulation and test datasets, including performance metrics such as measurement accuracy, latency, and throughput.
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Strong communication skills, both written and oral, with the ability to work effectively across cross-functional teams.
Preferred Qualifications
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Master's degree with 10 years of relevant experience.
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Hands-on experience in wireless chip or modem development, with a strong systems-level understanding of cross-layer dependencies between RF, PHY, MAC, and firmware.
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Hands-on experience in Bluetooth and UWB systems design and validation.
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Digital design fundamentals and a solid understanding of SoC architecture and system-level hardware/software interaction.
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Hands-on RTL experience (Verilog/VHDL) and experience with register map and programming-model definition.
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Experience with fixed-point design, RTL vector generation, and/or High-Level Synthesis (HLS).
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Experience with pre-silicon emulation (e.g., Palladium) or FPGA prototyping, including build bring-up, debug, and performance characterization.
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Experience developing validation frameworks and infrastructure, including initialization sequences, clock and reset setup, and system-level configuration.
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Experience in lab FPGA/silicon bring-up, PHY/RF/MAC testing, and use of RF lab equipment.
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Proficiency with Python for test automation and data analysis, and experience with simulation automation, regression frameworks, or CI/CD pipelines.
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Experience collaborating with firmware and FPGA/emulation engineers to bring up, integrate, and debug hardware platforms, ensuring correct hardware/software interaction.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
How this job compares
Set against the 11,546 open Systems Engineer jobs on Olive Jobs, counted November 4, 2026.
- Pay
- This postingNot listed
- California median$143–211K/yr1,759 salary ranges
- California median$70–90/hr56 hourly ranges
- Openings
- Olive Jobs lists 2,074 open Systems Engineer jobs in California and 11,546 across the US. 5% of them nationwide are listed as remote or flexible.
- Hiring the most in California
- Northrop Grumman210 open
- Anduril Industries139 open
- Anduril105 open
- Experience
- This posting asks for at least 10 years of experience — more than three in four Systems Engineer postings that state a minimum ask for (median 5 years, across 9,622 postings).
- Education
- This posting asks for a bachelor's degree; 4,535 of the 11,546 open Systems Engineer jobs (39%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on November 4, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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