High-Speed Peripheral Firmware Lead
San Jose, CAFull-timePosted todayStill listed today
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Job overview
Etched seeks a hands-on technical lead to develop firmware for high-speed peripherals on its custom AI accelerator. The role spans firmware architecture and implementation from early hardware design through pre-silicon validation, first-silicon bring-up, and production. The lead will collaborate with ASIC architects and RTL engineers, guide technical direction and reviews, and mentor engineers while remaining involved in implementation and debugging.
Skills & qualifications
Skills
Qualifications
Benefits
Full job description
About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary Lead the development of firmware that brings the high-speed peripherals of our custom AI accelerator to life. You and the team will own the low-level firmware responsible for controlling, configuring, and monitoring critical hardware interfaces, including PCIe, HBM, Ethernet, and other peripherals within our ASIC. You'll work directly with ASIC architects and RTL engineers from early hardware design through pre-silicon development, first-silicon bring-up, and production. The team is responsible for making these interfaces work reliably and at their full performance potential, while helping shape the hardware/software architecture of future silicon generations. This is a deeply hands-on technical leadership role for someone who enjoys building low-level software, solving difficult hardware problems, and taking ownership of critical parts of a new compute platform.
Key Responsibilities
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Lead a team developing low-level firmware to control, configure, and monitor PCIe, HBM, Ethernet, and other high-speed peripherals on our custom ASIC.
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Own the firmware architecture and implementation for these hardware blocks, from early design through silicon bring-up and production.
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Develop and validate firmware in simulation and emulation environments before silicon is available.
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Work directly with ASIC architects and RTL engineers to define hardware/software interfaces, influence design decisions, and debug complex integration issues.
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Bring up new peripheral blocks on first silicon, diagnose hardware and firmware issues, and drive them to resolution.
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Optimize peripheral configurations and firmware behavior to maximize performance and reliability.
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Set technical direction for the team, drive design and code reviews, and mentor engineers while staying deeply involved in implementation and debugging.
You may be a good fit if you have
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Bachelor's degree or equivalent practical experience.
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Strong C/C++ programming skills and low-level software engineering fundamentals.
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Experience developing firmware or drivers that interact directly with hardware.
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Experience working with ASICs, SoCs, embedded processors, or complex hardware platforms.
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Deep technical knowledge of at least one high-speed interface, such as PCIe, HBM, Ethernet, or a similar peripheral.
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Experience with hardware initialization, register-level programming, and debugging hardware/software interactions.
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Strong understanding of computer architecture, memory systems, concurrency, and performance.
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Experience owning complex firmware components and making technical design decisions.
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Ability to work closely with ASIC architects, RTL engineers, and hardware validation teams.
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Experience providing technical direction, reviewing designs, and mentoring other engineers.
Strong candidates may also have experience with (Nice-to-have qualifications)
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Pre-silicon firmware development using simulation, emulation, or FPGA platforms.
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First-silicon bring-up of custom ASICs, SoCs, GPUs, or other complex chips.
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Firmware development for PCIe, HBM, Ethernet, memory controllers, or high-speed interconnects.
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Hardware/software co-design, including defining register interfaces and firmware requirements alongside RTL teams.
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Debugging complex issues involving hardware initialization, data movement, synchronization, or peripheral performance.
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Experience optimizing firmware and hardware configurations for latency, throughput, and reliability.
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Building low-level firmware or driver architectures that support multiple silicon generations.
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Experience leading small, highly technical engineering teams while remaining hands-on.
Benefits
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Medical, dental, and vision packages with generous premium coverage
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$500 per month credit for waiving medical benefits
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Housing subsidy of $2.5k per month for those living within walking distance of the office
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Relocation support for those moving to San Jose (Santana Row)
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Various wellness benefits covering fitness, mental health, and more
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Daily lunch + dinner in our office
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Unlimited compute budget subject to ROI justification
How we're different Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
How this job compares
Set against the 2,287 open Engineering Leadership jobs on Olive Jobs, counted November 12, 2026.
- Pay
- This postingNot listed
- California median$209–316K/yr268 salary ranges
- Openings
- Olive Jobs lists 312 open Engineering Leadership jobs in California and 2,287 across the US. 6% of them nationwide are listed as remote or flexible.
- Experience
- Engineering Leadership postings that state a minimum ask for 10 years of experience at the median; the middle half ask for 8 to 14 years (1,790 postings).
- Education
- 718 of the 2,287 open Engineering Leadership jobs (31%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on November 12, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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