Front End Design Engineer
Austin, TXFull-timeSeen todaySeen in employer's feed today
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Job overview
Apple seeks a Front End Design Engineer in Austin, Texas. The role converts RTL designs into netlists, optimizes power, performance, and area, and evaluates RTL through timing, lint, crossing, and equivalence checks. The engineer analyzes simulation waveforms, supports ECO generation, and collaborates with internal R&D teams. A master's degree in a specified engineering field and one year of relevant experience are required.
Skills & qualifications
Skills
Qualifications
Full job description
Weekly Hours: 40
Role Number: 200691298-0157
Summary
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
Description
APPLE INC has the following available in Austin, Texas. Convert RTL designs into netlists using industry-standard RTL synthesis tools. Optimize power, performance, and area by experimenting with synthesis recipes and enhancing existing synthesis methodologies. Understand RTL code written in Verilog and SystemVerilog languages, correlate it to gate-level circuits, and guide the development of optimal RTL solutions. Perform Clock and Reset Domain Crossing (CDC,RDC) checks to ensure the design's robustness against metastability-related problems and lint checks. Perform logical equivalence checks to ensure correctness of the generated netlist and support ECO generation activities. Perform static timing analysis (STA) to identify critical paths in the design, then propose solutions spanning both physical implementation and microarchitectural optimizations. Analyze RTL simulation waveforms using industry standard simulator tools to understand the design's intent and common signal activity pattern. Lint checks to ensure the overall quality of RTL code. Collaborate effectively with internal R&D teams. 40 hours/week.
Minimum Qualifications
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Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field and 1 year of experience in the job offered or related occupation.
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Experience and/or education must include:
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Synthesizing RTL designs using Design Compiler/Genus into netlist
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Understanding RTL and make RTL updates for PPA
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Creating unit testbench to verify RTL updates
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Working with simulation waveform to understand design intent
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Performing Static Timing Analysis (STA) and achieving timing closure
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Performing Lint checks to ensure RTL quality
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Performing Clock Domain Crossing checks (CDC)
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Performing Reset Domain Crossing Checks (RDC)
Preferred Qualifications
- N/A
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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