
Staff Design Engineer (10476)
Hillsboro, ORJobSeen 5 days agoSeen in employer's feed 5 days ago
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At a glance
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Job overview
Qorvo designs RF solutions for wireless devices, networks, and other applications. The RFIC Design Engineer designs front-end modules for mobile wireless applications, including low-noise amplifiers and switches, and works with engineering, marketing, and cross-functional teams to develop products through production release. The role requires an MSEE with five or more years of directly applicable experience, or a PhD degree.
Skills & qualifications
Skills
Qualifications
Full job description
Qorvo is All Around You! We manufacture innovative RF solutions at the center of connectivity to enable high-performance applications for advanced wireless devices, wired and wireless networks and defense radar and communications for 5G networks, cloud computing, the Internet of Things, and other emerging applications. Our people are always at the core of Qorvo's innovation. Qorvo is a place to stretch your imagination and push boundaries to achieve success. We are looking for a motivated RFIC Design Engineer with a solid background in RF design, excellent communication skills, and strong drive to produce best in class products. The candidate will be responsible for designing RF front end modules for mobile wireless applications. The tasks include RF design of LNA's and switches, including module integration. The candidate will work closely with a core design engineering team and other cross functional team members to bring cutting edge wireless products to the market. RESPONSIBILITIES: Perform detailed, transistor-level RFIC design and product development focusing on low-noise amplifiers (LNA), switches, and/or integrated modules for mobile wireless applications using cutting edge technologies. Work with engineering and marketing managers to define product requirements. Create and execute product development plans including design, simulation, layout, and verification testing Work with cross-functional team members to bring products from conception to full production release. Support RFIC design integration into a multi-chip module (MCM). Use of RF measurement equipment with the ability to troubleshoot measurement issues. Documentation and presentation of results to internal and external customers such as conducting peer reviews of their designs, including expected and/or actual results QUALIFICATIONS: Demonstrated history of successfully designing and releasing to production state-of-the art RFIC's in RF CMOS, RF SOI and/or BiCMOS technologies. Proficiency with RFIC EDA tools such as Cadence and Keysight ADS Experience with EM simulators such as HFSS, FEM, and/or ADS Momentum. Experience with various linear and nonlinear simulation techniques and simulators. Detailed transistor-level knowledge of RF and microwave integrated circuit design techniques including RF switching, low noise amplifiers, bias circuits, and multi-chip module design. Ability to work in a fast paced, highly motivated and very interactive team environment. Effectively communicate ideas and progress status in presentations and written reports. Able to work independently and in teams. MSEE with 5+ years of directly applicable experience; or PhD degree.
How this job compares
Set against the 2,849 open Design Engineer jobs on Olive Jobs, counted October 27, 2026.
- Pay
- This postingNot listed
- US median$110–160K/yr1,817 salary ranges
- US median$43–55/hr97 hourly ranges
- Openings
- Olive Jobs lists 33 open Design Engineer jobs in Oregon and 2,849 across the US. 4% of them nationwide are listed as remote or flexible.
- Experience
- This posting asks for at least 5 years of experience; Design Engineer postings that state a minimum ask for 5 years at the median (2,308 postings).
- Education
- 2,086 of the 2,849 open Design Engineer jobs (73%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on October 27, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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