Physical Design Engineer II
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At a glance
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Job overview
The Physical Design Engineer II performs physical design at block, sub-chip, or full-chip level, including planning, synthesis, placement, clocking, timing analysis, and verification. The role develops electromigration and IR-drop signoff methodology, drives convergence of timing and EMIR issues, and delivers place-and-route strategies for challenging blocks. It also requires working with limited direction and communicating progress, issues, and risks to management.
Skills & qualifications
Skills
Qualifications
Full job description
Responsible for Physical Design tasks at block, sub-chip, and/or full-chip level incl. design planning, synthesis, placement, clock tree synthesis, custom clocking, static timing analysis, physical verification, IR drop & EM check and formal equivalence checks Responsible for delivering high-quality Electromigration and IR drop sign off modeling methodology and drive the overall EMIR convergence strategies To analyze and drive the Static Timing Analysis violations and its convergence To deliver best in class place and route (PNR) strategies especially on congestion and timing challenging blocks You are expected to be able to work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team. Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience. 4+ years of experience in Physical Design, especially in synthesis, place and route (PNR) and signoff 4+ years of hands-on experience in EDA vendor tools such as RHSC, Star-RC, Fusion Compiler, VCLP, Primetime, Formality, or Cadence Innovus and Conformal
How this job compares
Set against the 3,007 open Hardware Engineer jobs on Olive Jobs, counted November 5, 2026.
- Pay
- This postingNot listed
- Oregon median$154–235K/yr30 salary ranges
- US median$60–68/hr77 hourly ranges
- Openings
- Olive Jobs lists 52 open Hardware Engineer jobs in Oregon and 3,007 across the US. Under 1% of them nationwide are listed as remote or flexible.
- Experience
- This posting asks for at least 4 years of experience; Hardware Engineer postings that state a minimum ask for 5 years at the median (2,544 postings).
- Education
- 1,752 of the 3,007 open Hardware Engineer jobs (58%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on November 5, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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