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Staff Design Verification Engineer

Renesas

Plano, TXJobSeen 1w agoSeen in employer's feed 5 days ago

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At a glance

Compensation
No compensation found
Location
Plano, TX
Work Authorization
Not specified

Olive lists jobs from US employers, including remote roles you can work from the United States.

Requirements

Credentials this posting asks for.

Master's degree

Job overview

Renesas seeks an experienced Staff Verification Engineer to verify and model mixed-signal automotive power-management devices, including PMICs, switching regulators, and analog IP. The engineer works with design, systems, validation, and CAD teams to develop and sign off complex power chips. The role includes verification architecture, simulation, debugging, and cross-functional handoffs.

Skills & qualifications

RequiredNice to have

Skills

Mixed-Signal VerificationVerification ArchitectureRNM IntegrationAMS IntegrationSpectreXceliumRTL SimulationBehavioral SimulationGLS FlowsAnalog DebuggingDigital RTL DebuggingAutomotive PMIC VerificationVerilogSystemVerilogSPICEUVMAssertionsCoverage-Driven VerificationATE Test CorrelationProblem-SolvingAnalytical ThinkingLeadershipMentoring

Qualifications

MS or PhD in Electrical Engineering, Computer Engineering, or Related Field8+ Years Mixed-Signal or Analog Verification Experience

Full job description

Staff Design Verification Engineer

Job Description

Renesas is seeking an experienced Staff Verification Engineer. As mixed-mixed signal verification engineer you will be responsible for the verification and modeling of mixed-signal Automotive power management devices, including PMICs, switching regulators, and related analog IP. You will work closely with design, systems, validation, and CAD teams to drive successful development, integration, and sign-off of complex mixed-signal power chips.

Key Responsibilities

  • Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration for PMIC designs

  • Develop and implement comprehensive verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200)

  • Lead debugging activities for complex analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces

  • Set up and optimize Gate-Level Simulation (GLS) flows, correlating with RTL simulation results to identify and resolve discrepancies

  • Conduct in-depth RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners

  • Collaborate closely with cross-functional teams: Design, Application Engineering, ATE (Automatic Test Equipment), and Silicon Validation to ensure seamless verification handoffs

  • Troubleshoot and debug complex design issues involving interactions between analog and digital domains using simulation and measurement techniques

  • Drive continuous improvement of verification tools, methodologies, and infrastructure, evaluating emerging verification technologies and AI-based solutions

  • Create and maintain comprehensive verification documentation, test plans, and coverage metrics

Qualifications

  • MS or PhD in Electrical Engineering, Computer Engineering, or related field

  • 8+ years of experience in mixed-signal or analog circuit verification

  • Deep understanding of all aspects of mixed-signal verification environment architecture and implementation

  • Hands-on experience with Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration

  • Proficiency in RTL and behavioral simulation tools (e.g., Spectre, Xcelium)

  • Strong understanding of Gate-Level Simulation (GLS) flows and ability to set up and debug GLS simulations

  • Proven expertise debugging both analog blocks (switched-mode regulators, LDO, bandgap, reference circuits) and digital RTL

  • Experience with automotive PMIC or power management IC design and verification

  • Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages

  • Solid understanding of verification methodologies: UVM, assertions, coverage-driven verification

  • Experience interfacing with multiple verification domains: functional, post-silicon, ATE test correlation

  • Excellent problem-solving and debugging skills with strong analytical mindset

  • Leadership and mentoring experience

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement (https://jobs.renesas.com/diversity-and-inclusion) .

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.

VideoUrl

https://www.youtube.com/watch?v=k-zs4tB6nNc&t=15s

  1. Department Engineering

  2. Location Plano

  3. Remote No

Requisition ID

20026120_2026-03-16

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How this job compares

Set against the 323 open Verification Engineer jobs on Olive Jobs, counted November 3, 2026.

Pay
  • This postingNot listed
  • US median$131–215K/yr200 salary ranges
Openings
Olive Jobs lists 49 open Verification Engineer jobs in Texas and 323 across the US. 2% of them nationwide are listed as remote or flexible.
Hiring the most in Texas
Experience
This posting asks for at least 8 years of experience; Verification Engineer postings that state a minimum ask for 5 years at the median (278 postings).
Education
This posting asks for a master's degree; 16 of the 323 open Verification Engineer jobs (5%) ask for a master's degree or higher.

Counted across the open, public US postings on Olive Jobs on November 3, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.

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