CAD Engineer – EMIR Signoff
Sunnyvale, CAJobSeen 4w agoSeen in employer's feed 1w ago
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Job overview
As a Signoff Engineer on Apple’s advanced Signoff CAD team, the hire will verify and analyze complex mixed-signal designs before tapeout, developing signoff methodologies for power and EMIR analysis at gate and transistor levels. The role includes defining signoff requirements, confirming EDA flows and tools with partner teams, meeting project signoff criteria, and supporting design groups. The team is exploring AI/ML and LLM-driven approaches to accelerate analysis and identify anomalies.
Skills & qualifications
Skills
Qualifications
Full job description
Role Number: 200687318-3956
Summary
Do you love building elegant solutions to highly complex challenges? Do you believe every detail matters? As part of our Silicon Technologies group, you’ll help design and manufacture Apple’s next-generation, high-performance, power-efficient system-on-chip (SoC) processors — the technology that lets Apple products and services handle everything our customers love doing with their devices, seamlessly and efficiently.
Description
As a Signoff Engineer, you’ll ensure that all necessary verification and analysis work is completed on complex mixed-signal designs prior to tapeout. In this highly visible role on our advanced Signoff CAD team, you’ll work on state-of-the-art designs and apply hands-on experience in power/EMIR analysis to develop, define, and refine signoff methodologies at both the gate and transistor level. This includes, but isn’t limited to, signoff for functional static/dynamic IR analysis, scan-mode IVD analysis, package model handling, power EM analysis, signal EM, power switch modeling, and IP reuse. Our team is also evolving how we approach signoff itself — increasingly exploring AI/ML and LLM-driven techniques to accelerate analysis, automate flow debugging, and surface anomalies earlier in the design cycle.
You’ll help define signoff requirements early in the project lifecycle, partner with Design, CAD, and Technology teams to confirm EDA flows and tools are set up and running correctly, and ensure all signoff criteria are met by project close. You’ll also interface directly with design groups, providing frontline support for enablement, enhancement, and debug requests.
Minimum Qualifications
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Minimum requirement of BS and 3+ years of relevant industry experience
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Experience in CAD, EMIR analysis, or related circuit design roles
Preferred Qualifications
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Solid understanding of circuit design principles and EMIR analysis at the transistor and gate level, across multiple modes (static and dynamic)
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In-depth knowledge of industry-leading tools such as Redhawk, Voltus, and Totem
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Experience in simulation and power analysis to verify circuit performance
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Strong understanding of CAD flows
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Proficiency in scripting/programming languages (Perl and Python)
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Excellent communication and collaboration skills
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Experience developing CMOS analog and mixed-signal designs
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Experience applying AI/ML or LLM-based tools to EDA flow automation, anomaly detection, or signoff data analysis
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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