ASIC Engineer, Formal Verification
Sunnyvale, CAJob$178–250K/yrSeen 3 days agoSeen in employer's feed 3 days ago
Most applications go out cold — see where you stand first. No sign-up to start.
Watch jobs like this. New roles like this one near Sunnyvale, CA, by email.
Don't just apply. Show up ready.
Olive works from this exact posting.
At a glance
Olive lists jobs from US employers, including remote roles you can work from the United States.
Job overview
Meta is hiring an ASIC Formal Verification Engineer in its Infrastructure organization to build IP and SoCs for data center applications. The engineer will develop formal test plans and own verification sign-off for complex blocks, collaborating with software, hardware, ASIC design, emulation, and post-silicon teams. The role also involves shaping formal verification methodology, building reusable environments, evaluating EDA solutions, and mentoring internal engineers.
Skills & qualifications
Skills
Qualifications
Full job description
Summary:
Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing innovative ASIC solutions for Meta’s data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
Required Skills:
ASIC Engineer, Formal Verification Responsibilities:
-
Provide technical leadership in Formal Verification
-
Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level
-
Work with Architecture and Design team to come up with formal specification and implementation
-
Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level
-
Build reusable/scalable environments for Formal Verification and deploying the tools
-
Evaluate and recommend EDA solutions for Formal Verification
-
Provide training for internal teams and mentoring engineers on Formal Verification technology related to Formal Verification Technology
Minimum Qualifications:
Minimum Qualifications:
-
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
-
8+ years of experience in Design Verification
-
5+ years of experience in Formal Verification
-
Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
-
Proven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniques
-
Proven analytical skills to craft novel solutions to tackle industry-level complex designs
-
Experience collaborating with cross-functional teams such as design, architecture, and software to deliver verification milestones
-
Fluency in hardware description languages, such as SystemVerilog and SVA
-
Proficiency in scripting languages such as Python, Perl, or Tcl
-
Experience with JasperGold or VC-Formal
Preferred Qualifications:
Preferred Qualifications:
-
Experience with development of fully automated flows from specification to fully verified designs
-
Experience interpreting hardware specifications and extracting design behaviors and properties for formal verification
-
Experience with complex SoCs
-
Formal verification experience in clock domain crossing, IP-XACT based register verification and low power
-
Experience with simulators and waveform debugging tools
-
Experience in formal property verification of complex compute blocks such as DSP, CPU, GPU or HW accelerators
Public Compensation:
$178,000/year to $250,000/year + bonus + equity + benefits
Industry: Internet
Equal Opportunity:
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].
Similar jobs, posted recently
Open roles like this one, listed in the last 30 days.
Principal Design Verification Engineer - FormalMicrosoft Corporation · Mountain View, CA · $143–275K/yrPosted 2w agoPosted 2w ago- Formal Verification EngineerTenstorrent · Remote · US · $100–500K/yrPosted 3w agoPosted 3w ago
Senior ASIC Design Verification EngineerCisco · San Jose, CA · $168–245K/yrPosted 6 days agoPosted 6 days ago
Senior ASIC Design Verification Engineer, CloudGoogle · Sunnyvale, CA · $163–236K/yr
Senior ASIC Design Verification EngineerPalo Alto Networks · CA · $129–209K/yrPosted 1w agoPosted 1w ago
You've read the whole posting — now see how you match it.