Qorvo US, Inc. logo

Staff CAD Engineer (10769)

Qorvo US, Inc.

Newbury Park, CAJobSeen 1w agoSeen in employer's feed today

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At a glance

Compensation
No compensation found
Location
Newbury Park, CA
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

IPC Certification

Job overview

The Staff ECAD Engineer leads PCB design and fabrication across high-performance RF and power product lines. The role sets design standards, resolves complex signal- and power-integrity challenges, and guides quality improvements across programs. It provides technical direction and mentorship while partnering with engineering teams and suppliers from concept through manufacturing.

Skills & qualifications

RequiredNice to have

Skills

PCB DesignSchematic CapturePCB LayoutIPC StandardsAltiumCadence AllegroADSAutoCADSolidWorksCAM350PCB ManufacturingGD&TDFM/DFA/DFT/DFRRF DesignHigh-Frequency LaminatesCadence SigritySI/PI/EM SimulationTransmission Line TheoryImpedance ControlSignal PropagationCrosstalkTermination MethodsPDNGroundingSI/PI AnalysisMicrosoft OfficeEngineering DocumentationPLM SystemsWritten CommunicationVerbal CommunicationPriority Management

Qualifications

Bachelor's in Electrical Engineering, Electronic Engineering, Materials Science or Related Field or Equivalent Experience15+ Years PCB/PWB ExperienceIPC Certification

Full job description

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet. Position Summary The Staff ECAD Engineer is the technical lead for PCB design and fabrication across all high performance RF and power product lines, combining master level CAD/layout expertise with deep IPC knowledge. This individual contributor role sets standards and design rules, resolves the most complex signal integrity, power integrity, and reliability challenges, and drives quality improvements across programs. The role leads through influence, mentoring Staff and Senior engineers and setting technical direction. # Key Responsibilities - Independently execute end-to-end PCB design using Altium or Cadence tools, including schematic capture and complex PCB layout, from concept to fabrication, assembly, and production builds. - Set standards, design rules, and IPC compliance practices. Provide sign-off on complex, high frequency PCB designs and fabrication documentation (Altium, Cadence Allegro, ADS, SolidWorks, AutoCAD). - Lead root cause investigation and corrective action for design/fabrication issues involving IPC standards, signal integrity, thermal, and mechanical interactions. - Provide expert DFM/stack-up guidance from concept through NPI, partnering with RF, Mechanical, Component, and Process Engineering. - Mentor Staff and Senior engineers as a technical resource and design reviewer across programs. - Perform pre and post layout SI/PI/EM analysis (Cadence Sigrity or equivalent tools) to validate high speed and high frequency designs. - Develop transmission line models, impedance controlled routing, crosstalk, and PDN analysis; drive simulation based optimization for DDR4/DDR5, PCIe, SerDes, Ethernet, USB, and RF interfaces. - Present simulation findings and risk mitigation recommendations at design reviews. - Apply HDI techniques for high pin count, fine pitch BGA routing on complex multilayer boards. - Apply DFx methodologies (DFM, DFA, DFT, DFR) to ensure manufacturability, testability, and reliability. - Partner with Hardware, Mechanical, Procurement, Manufacturing, and Program Management to align designs with product requirements and schedules. - Work with suppliers to improve process capability, yield, cycle time, cost, and support qualification and audits of RF/high frequency fabrication partners. - Prepare and manage complete design documentation packages, including fabrication and assembly drawings, Gerber files, BOMs, and Engineering Change Orders (ECOs), ensuring accuracy and traceability with timely release and smooth transition into manufacturing, while collaborating closely with cross functional stakeholders. - Manage the lifecycle of Technical Queries (TQs), ensuring timely resolution and clear communication. # Required Qualifications - Bachelor's degree in Electrical Engineering, Electronic Engineering, Materials Science, or related field; equivalent extensive practical experience considered in lieu of degree. - 15+ years of combined experience in PCB/PWB design, CAD layout, and/or fabrication/supplier development, with demonstrated progression into a senior technical role. IPC certification(s) required. - Deep proficiency with ECAD/mechanical CAD tools: Altium, Cadence Allegro, ADS, AutoCAD, SolidWorks, and CAM350. - Extensive hands on kn wledge of PCB/PWB manufacturing processes, materials, and IPC standards, with proven application of GDandT and DFM/DFA/DFT/DFR principles. - Strong RF/high frequency design background, including high frequency laminates (Rogers, PTFE/Teflon) and demanding applications such as ATE multisite load boards and probe cards. - Hands on experience with Cadence Sigrity or equivalent program and related SI/PI/EM simulation environments. - Strong understanding of transmission line theory, impedance control, signal propagation, reflection, crosstalk, termination methods, PDN, and grounding. - Experience with pre and post layout SI/PI analysis for DDR4/DDR5, PCIe, Ethernet, USB, SerDes, and high-speed ATE applications. - Excellent written/verbal communication skills, including presenting technical findings to cross functional audiences. - Proficiency with Microsoft Office and engineering documentation/PLM systems. - Ability to independently manage competing priorities across multiple concurrent programs. ::: {style="color: #000000; background-color: #ffffff; margin: 0in 0in 0in 0px; f "} :::

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