
Sr Test Engineer (10461)
San Jose, CAJobSeen 1w agoSeen in employer's feed 1w ago
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At a glance
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Job overview
Qorvo is seeking a Senior Test Engineer to build and maintain wafer- and package-level RF-MEMS test infrastructure. The role develops automated test programs, leads validation and qualification strategies, debugs test systems, and supports manufacturing ramp into production. It collaborates with RF and MEMS design, process engineering, reliability, and product engineering teams.
Skills & qualifications
Skills
Qualifications
Full job description
Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet. Key Responsibilities - Build test infrastructure for wafer-level and package-level RF-MEMS testing, including probe-station setups, RF/DC benches, and automated test equipment. - Develop and maintain automated test programs using LabVIEW, NI TestStand, and C#, ensuring scalability, repeatability, and production readiness. - Lead validation strategy, defining test plans, characterization matrices, DOE structures, and qualification flows. - Debug test programs, instrument communication, and hardware setups, resolving measurement anomalies and repeatability issues. - Design, qualify, and maintain probe cards for wafer-level RF-MEMS testing. - Support manufacturing ramp, transitioning test programs and hardware into production environments and improving throughput. - Collaborate cross-functionally with RF design, MEMS design, process engineering, reliability, and product engineering teams. Required Skills and Experience Software and Automation - Strong experience with LabVIEW for custom measurement routines. - Expertise in NI TestStand for sequencing, reporting, and production deployment. - Proficiency in C# for instrument drivers, automation frameworks, and UI tools. Hardware and Debugging - Wafer-level RF/DC testing experience, including probe-station workflows, and tester calibration. - Experience with motherboard/PCB design or layout, including RF routing and signal integrity. - Ability to read and interpret schematics for test boards, probe cards, and driver circuits. - Hands-on debugging of test programs, hardware bring-up, and instrument communication. - Experience with probe card design, qualification, and maintenance. Professional Background - Typically 5+ years in semiconductor test engineering, RF test, MEMS test, or mixed-signal ATE development. - Experience supporting both RandD characterization and production test environments. - Demonstrated ownership of test infrastructure or validation strategy. Education - - BS/MS/PhD in Electrical Engineering, Computer Science, or related field. ::: {style="color: #000000; background-color: #ffffff; margin-top: 0in; margin-right: 0in; mar "} :::
How this job compares
Set against the 563 open Test Engineering jobs on Olive Jobs, counted October 30, 2026.
- Pay
- This postingNot listed
- California median$146–196K/yr101 salary ranges
- California median$30–40/hr23 hourly ranges
- Openings
- Olive Jobs lists 151 open Test Engineering jobs in California and 563 across the US. 1% of them nationwide are listed as remote or flexible.
- Hiring the most in California
- Anduril16 open
- Anduril Industries10 open
- Northrop Grumman10 open
- Experience
- This posting asks for at least 5 years of experience; Test Engineering postings that state a minimum ask for 5 years at the median (416 postings).
- Education
- 244 of the 563 open Test Engineering jobs (43%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on October 30, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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