Signal & Power Integrity (SI/PI) Engineer – Advanced Packaging

CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

The Role

This position owns the electrical performance of CScale optical engine packages across three areas: signal integrity between the electronic IC and the photonic dies inside the package; signal integrity across the channel between the CScale package and the host ASIC; and power integrity for the package as a whole. This role defines the modeling and measurement approach as much as it applies one.

You will drive the electrical definition of the package architecture rather than validate a design handed to you after floorplan freeze.

Responsibilities

3D EM modeling and correlation

• Perform 3D EM design and simulation of high-speed interconnects.

• Model and characterize in-package interconnect between the electronic IC and the photonic dies, including transition structures.

• Develop and validate test vehicles to characterize next-generation PCB materials, packages, and interconnects.

• Conduct S-parameter and time-domain measurement to extract channel performance and correlate against simulation.

Channel architecture and standards compliance

• Perform link-level analysis against advanced high-speed standards, and design package substrate stackups, via structures, breakout regions, and connector transitions to meet IEEE, CEI, and MSA compliance.

• Define routing constraints, reference plane design, and return path continuity to hold signal degradation within budget.

Power delivery

• Design and optimize PDNs to meet target impedance, minimize noise coupling, and support fast transient loads for high-speed DSPs and ICs.

Design collaboration and bring-up

• Work with CMOS design, optical, and packaging teams to converge stack-up, breakout, and routing strategy for high-density designs without sacrificing manufacturability or reliability.

• Provide SI/PI layout guidelines to package substrate designers, and review placement and routing on high-speed paths and power domains before release.

• Support bring-up and validation.

Required Qualifications

• BS or higher in Electrical Engineering, Applied Physics, or a related field, with emphasis on electromagnetics, signal integrity, power integrity, or high-speed digital design.

• 7+ years of package-level SI/PI analysis experience on high-speed interconnects in optical, networking, or high-performance hardware systems.

• Hands-on proficiency with 2.5D/3D EM solvers: Ansys HFSS, SiWave, Cadence Sigrity, CST, or Keysight ADS.

• Command of signal integrity fundamentals, including S-parameter analysis and channel modeling.

• High-speed differential signal integrity at 224G or similar.

• Working knowledge of PCB and package substrate stackup design, via modeling, impedance control, and crosstalk mitigation.

• Working knowledge of power delivery design: decoupling strategy, PDN impedance analysis, and noise mitigation.

Preferred Qualifications

• Co-packaged optics or interposer-structure package experience.

• Custom model and workflow development for EM simulation or measurement automation.

• 2.5D/3D package architecture experience extending beyond interconnect-level SI/PI.

• 448G signaling, or UCIe or similar die-to-die interfaces