
CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate)
Austin, TXFull-time$86–170K/yrSeen 3 days agoSeen in employer's feed 3 days ago
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At a glance
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Job overview
GlobalFoundries seeks a new college graduate to develop and verify advanced RISC-V processor IP on its MIPS CPU IP Engineering team. The role involves CPU microarchitecture, SystemVerilog RTL, functional verification, power, performance, and area analysis, plus automation and debug. The position is based in Austin, Texas or Santa Clara, California, and is intended for graduates with a degree in a related engineering field.
Skills & qualifications
Skills
Qualifications
Full job description
USA - Texas - Austin
USA - California - Santa Clara
Full time
JR-2604136
About GlobalFoundries
GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, powerefficient and highperformance solutions for highgrowth markets. GF is a trusted and holistic technology partner for customers around the world. GF’s talented, global team remains focused every day on security, longevity and sustainability. For more information, visit www.gf.com.
New College Graduates Overview:
We offer many full-time employment paths for recent graduates, which provide accelerated training in a fast-paced work environment, cross-functional working opportunities, and talent mobility. New college graduates are provided with mentorship, networking, and leadership opportunities, which give our new team members life-long connections and skills.
Summary of Role:
GlobalFoundries is seeking a New College Graduate CPU IP Design & Verification Engineer to join the MIPS CPU IP Engineering team and develop and verify advanced RISC-V processor IP. The role provides hands-on experience in CPU microarchitecture, SystemVerilog RTL implementation, functional verification, power, performance, and area analysis, automation, and debug in Austin, Texas or Santa Clara, California.Essential Responsibilities include:
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Design and develop RISC-V CPU microarchitecture and SystemVerilog RTL design and development.
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Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts.
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Develop verification tests, assertions, checkers, and functional coverage for CPU features.
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Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms.
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Support functional and coverage closure through design and verification reviews.
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Support CPU power, performance, and area analysis and optimization.
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Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity.
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Collaborate across architecture, design, verification, performance, and implementation teams to deliver high-quality CPU IP.
Other Responsibilities:
- Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Required Qualifications:
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Education – Graduating with a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field from an accredited degree program.
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Must have at least an overall 3.0 GPA and proven good academic standing.
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Language Fluency - English (Written & Verbal)
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Strong foundation in digital logic design and computer architecture.
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Coursework, research, internship, or project experience with Verilog or SystemVerilog.
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Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy.
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Programming or scripting experience with Python, C/C++, or similar languages.
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Strong analytical, problem-solving, and debugging skills.
Preferred Qualifications:
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Prior related internship or co-op experience.
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Demonstrated prior leadership experience in the workplace, school projects, competitions, etc.
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Project management skills, i.e. the ability to innovate and execute solutions that matter; the ability to navigate ambiguity.
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Strong written and verbal communication skills
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Strong planning & organizational skills
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Knowledge of the RISC-V Instruction Set Architecture (ISA).
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Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification.
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CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience.
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Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory.
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Experience with simulation, waveform debug, Git, and Linux.
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Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis.
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Assembly-language programming experience.
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Interest in using AI-assisted engineering tools to improve RTL design, verification, automation, and debug productivity.
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Expected Salary Range
$86,000.00 - $170,000.00
The exact Salary will be determined based on qualifications, experience and location.
If you need a reasonable accommodation for any part of the employment process, please contact us by email at [email protected] and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.
GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law
We shape what's essential
At GlobalFoundries you will find a vibrant work environment where collaboration and innovation thrive. Our diverse and global team shares a culture of respect and inclusivity, representing the best in the industry. We celebrate success together and are united by our dedication to excellence and our desire to improve and empower the world.
How this job compares
Set against the 348 open Verification Engineer jobs on Olive Jobs, counted October 27, 2026.
- Pay
- This posting$86–170K/yr
- Texas median$133–215K/yr20 salary ranges
- US median$136–219K/yr223 salary ranges
This range's midpoint, $128K, is 27% below the Texas median midpoint ($175K) — in the lowest quarter of Verification Engineer salary ranges in Texas.
- Openings
- Olive Jobs lists 54 open Verification Engineer jobs in Texas and 348 across the US. 1% of them nationwide are listed as remote or flexible.
- Experience
- Verification Engineer postings that state a minimum ask for 5 years of experience at the median; the middle half ask for 3 to 8 years (297 postings).
- Education
- 233 of the 348 open Verification Engineer jobs (67%) ask for a bachelor's degree or higher.
Counted across the open, public US postings on Olive Jobs on October 27, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.
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