Senior Wafer Test Hardware Engineer, Raxium

Senior Wafer Test Hardware Engineer, Raxium Share Senior Wafer Test Hardware Engineer, Raxium

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corporate_fareGoogleplaceFremont, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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Share Senior Wafer Test Hardware Engineer, Raxium

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Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.

• 5 years of experience in writing semiconductor functional tests, including register-level writes/reads and validation on production data.

• 2 years proven experience with wafer-level probe technologies, including troubleshooting and failure analysis.

• Experience validating hardware and software paths, including step-by-step component validation (e.g., verifying pin-to-pad contact and communication).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP).

• Experience with reliability hardware bring-up and qualification.

• Experience driving hardware specifications with external equipment vendors.

• Experience with data analysis and visualization tools such as JMP, Python, or SQL.

• Proficiency in structuring semiconductor test data streams, automating data ingestion and designing data visualizations or dashboards for operational monitoring.

• Ability to lead technical projects autonomously and drive alignment across teams (Hardware, Silicon design, Data/IS, and Manufacturing).

About the job Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability. Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google. Responsibilities

• Drive the specification process for a parallel wafer-level test tool, coordinating with internal teams on pad accommodations and initial bring-up plans.
• Define and execute the hardware/software validation path, verifying individual vendor components (such as single-die verification or pin-to-pad communication) independently from the complete solution.
• Assemble comprehensive test plans, including defining instruction sets for our unique displays.
• Define input and output data streams with vendors, and coordinate test and information systems (IS) infrastructure to manage and transfer massive die-level datasets.
• Define the operational flow, integrate the reliability tool with the manufacturing execution system (MES), and establish clear standard operating procedures (SOPs).

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