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Senior Verification Engineer

Retym, Inc

Austin, TXJobPosted 1w agoStill listed 4 days ago

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At a glance

Compensation
No compensation found
Location
Austin, TX
Work Authorization
Not specified

Olive lists jobs from US employers, including remote roles you can work from the United States.

Job overview

Retym is seeking a Senior Verification Engineer to drive RTL design verification for next-generation high-speed communication technology. The engineer will own block and cluster verification, lead testbench architecture and functional coverage planning, and collaborate with design, architecture, and algorithm teams. The role includes building verification environments, debugging functionality, and supporting and mentoring other engineers. Ethernet experience is preferred.

Skills & qualifications

RequiredNice to have

Skills

RTL VerificationTestbench ArchitectureFunctional CoverageVLSI VerificationData Path VerificationData ProtocolsEtherneteRMUVMSystemVerilogDigital Design VerificationCoverage CollectionDebuggingMentoring

Qualifications

10+ Years Experience2+ Verification Cycles

Full job description

For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects.

Requirements:

Key responsibilities:

  • Ownership of block\cluster verification end to end from scratch.
  • Lead efforts of test bench architecture, Vplan definition and functional coverage.
  • Work closely with the design, architecture, algo teams and other stakeholders.
  • Support other team members and mentor less experienced engineers.

Requirements

  • 10+ years of experience – a must
  • Performed at last 2 or more full block/system verification cycles.
  • In depth knowledge in VLSI verification flow, languages and concepts.
  • Experience in data path or data protocols, specifically Ethernet - preferred
  • Verification using one of the known methodologies (eRM, UVM).

Responsibilities

  • Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.
  • Build verification environments using SystemVerilog and UVM.
  • Identify and write all types of coverage measures for corner-cases.
  • Debug the functionality with design engineers.
  • Perform coverage collection and follow the metrices to close the full functionality.

How this job compares

Set against the 348 open Verification Engineer jobs on Olive Jobs, counted October 27, 2026.

Pay
  • This postingNot listed
  • Texas median$133–215K/yr20 salary ranges
Openings
Olive Jobs lists 54 open Verification Engineer jobs in Texas and 348 across the US. 1% of them nationwide are listed as remote or flexible.
Hiring the most in Texas
Experience
This posting asks for at least 10 years of experience — more than three in four Verification Engineer postings that state a minimum ask for (median 5 years, across 297 postings).
Education
233 of the 348 open Verification Engineer jobs (67%) ask for a bachelor's degree or higher.

Counted across the open, public US postings on Olive Jobs on October 27, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.

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