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Senior Principal Researcher - AI Systems Architecture

Yammer

Mountain View, CAJobPosted 2 days agoStill listed today

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At a glance

Compensation
No compensation found
Location
Mountain View, CA
Work Authorization
Not specified

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Job overview

The Senior Principal Researcher will lead end-to-end AI system, memory, and hardware architecture, connecting model execution behavior with platform capabilities. The role explores emerging AI workloads and next-generation hardware through pre-silicon modeling, feasibility analysis, and prototypes. It also evaluates system trade-offs, collaborates across research and product engineering, publishes research, mentors technical contributors, and transfers promising concepts toward deployment.

Skills & qualifications

RequiredNice to have

Skills

Computer ArchitectureMemory SystemsSilicon ArchitectureAI SystemsPlatform DesignHardware/Software Co-DesignSystem SoftwareMemory HierarchyInterconnectsPre-Silicon ArchitecturePerformance ModelingFeasibility AnalysisParallel Accelerator SystemsDRAMHBMCXLGPU Memory SystemsHost-Memory InterfacesHigh-Bandwidth Memory ArchitecturesAccelerator-Attached MemoryAdvanced Packaging2.5D/3D IntegrationHigh-Speed Scale-Up InterconnectsLLM InferenceLLM TrainingMixture-of-Experts RoutingKV-Cache BehaviorCycle-Accurate SimulatorsPerformance-Analysis InfrastructureSystem-Level OptimizationBandwidth AnalysisLatency AnalysisCapacity AnalysisLocality AnalysisPower AnalysisThermal AnalysisArea AnalysisData-Movement AnalysisResearchPatent Development

Qualifications

Doctorate or Master's or Bachelor's in CS, CE, EE or Related Field With Experience Alternatives6+ Years Related Research Experience7+ Years Related Research Experience9+ Years Related Research ExperiencePublication or Patent Record

Full job description

Lead end-to-end AI system, memory, and hardware architecture, identifying cross-layer opportunities across workloads, runtimes, memory systems, and hardware. Develop architectural abstractions and mechanisms that connect AI model execution behavior with platform capabilities. Analyze emerging AI workloads, including computation, memory access, communication, data movement, bandwidth, latency, capacity, and power requirements. Drive pre-silicon architectural exploration, performance modeling, feasibility analysis, and implementation pathfinding for next-generation AI hardware. Evaluate trade-offs across performance, bandwidth, latency, power, thermal limits, silicon area, packaging, and total cost of ownership. Build analytical models, simulators, prototypes, and experimental systems to validate architectural hypotheses. Collaborate across research and product engineering, publish research, mentor technical contributors, and transfer promising concepts toward deployment. Doctorate in Computer Science, Computer Engineering, Electrical Engineering, or relevant field AND 6+ years related research experience OR Master's Degree in Computer Science, Computer Engineering, Electrical Engineering, or relevant field AND 7+ years related research experience OR Bachelor's Degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field AND 9+ years related research experience OR equivalent experience. Extensive experience in computer architecture, memory systems, silicon architecture, AI systems, platform design, or hardware/software co-design. Experience reasoning across workload behavior, system software, memory hierarchy, interconnects, and hardware architecture. Experience with pre-silicon architecture definition, modeling, feasibility analysis, or highly parallel accelerator-based systems. Record of technical innovation demonstrated through research, patents, publications, prototypes, architecture delivery, or product deployment. Experience with DRAM, HBM, CXL, GPU memory systems, host-memory interfaces, or high-bandwidth memory architectures. Experience with accelerator-attached memory, advanced packaging, 2.5D/3D integration, or high-speed scale-up interconnects. Experience analyzing large AI workloads such as LLM inference or training, mixture-of-experts routing, and KV-cache behavior. Experience developing performance models, cycle-accurate simulators, prototypes, or performance-analysis infrastructure. Experience translating new memory or hardware capabilities into measurable system-level improvements. Experience evaluating bandwidth, latency, capacity, locality, power, thermal, area, and data-movement trade-offs. Publication or patent record in computer architecture, systems, memory systems, AI infrastructure, or hardware platforms. Experience collaborating across research, pre-silicon design, and product engineering organizations.

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