
Elect Design and Analy Engr 4
Mountain view``, CAContract$80–85/hrSeen 2 days agoSeen in employer's feed 2 days ago
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Job overview
PDS Defense seeks an Electrical Design and Analysis Engineer 4 in Mountain View, California. The role verifies ASICs and FPGAs using SystemVerilog and UVM, develops reusable testbench components, builds coverage models, and supports simulation, FPGA prototyping, and hardware integration. The posting lists a bachelor's degree or equivalent experience and describes preferred verification experience and additional preferred tools and domain knowledge.
Skills & qualifications
Skills
Qualifications
Benefits
Full job description
Engineering
Elect Design and Analy Engr 4 Mountain view``, CA Posted: 4/10/2026
Job Description
Job ID#:
216586
Job Category:
Engineering
Position Type:
Associate - W2
Shift:
1
PDS Defense, Inc. is seeking an Elect Design and Analy Engr 4, in Mountain View, CA.
Pay Rate: $80 - $85/hr
Job Description:
-
Write SystemVerilog/UVM testbenches to verify ASICs and FPGAs.
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Develop self-checking, reusable UVM components: drivers, monitors, scoreboards, sequencers.
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Build functional coverage models and close code coverage gaps.
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Create tests that verify DSP and third-party IP integration.
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Run simulations, linting, CDC checks, static timing checks, and gate-level regressions.
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Use scripting (Python/Perl/Make) and revision control (git/svn) to automate flows.
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Support FPGA bring-up, hardware emulation/prototyping, and hardware integration tests.
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Collaborate with system and hardware teams to capture requirements and debug issues.
Required Skills
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Bachelor's degree in EE, CE, CS, or related field (or equivalent experience).
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Experience with ASIC/FPGA verification using SystemVerilog and UVM.
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Ability to build self-checking testbenches and use object-oriented SV features.
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Familiarity with functional coverage and code coverage closure.
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Comfortable in Linux and using scripting tools.
Preferred Skills
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2+ years (Associate) or 5+ years (Experienced) verification experience.
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Experience with hardware emulators (e.g., Palladium) and FPGA prototyping.
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Knowledge of high-speed SerDes (PCIe, Ethernet, JESD204C).
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Experience with SVA (SystemVerilog Assertions) and RTL-to-GDS flows.
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Familiar with space/radiation mitigation techniques is a plus.
Education / Experience: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience (e.g. PhD+4 years' related work experience, Master+7 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Job Requirements
Minimum Security Clearance:
No Clearance
Military connected talent encouraged to apply.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
-
The California Fair Chance Act
-
Los Angeles City Fair Chance Ordinance
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Los Angeles County Fair Chance Ordinance for Employers
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San Francisco Fair Chance Ordinance
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
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