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ASIC Engineer, Design

Meta

Montgomery, ALJob$178–250K/yrSeen todaySeen in employer's feed today

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At a glance

Compensation
$178–250K/yr
Location
Montgomery, AL
Work Authorization
Not specified

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Job overview

Meta is hiring ASIC Design Engineers in its Infrastructure organization to build ASICs for areas including machine learning, video transcoding, and network acceleration. The role covers architecture exploration, micro-architecture development, IP selection and integration, collaboration on test planning and debugging, and design closure for timing and power. Minimum qualifications include a bachelor's degree or equivalent practical experience and at least eight years of relevant experience, or experience in SoC micro-architecture, design, and integration.

Skills & qualifications

RequiredNice to have

Skills

ASIC DesignArchitecture ExplorationMicro-ArchitectureRTL DevelopmentVerilogSystemVerilogHigh-Level SynthesisCPU SubsystemsNetwork-on-ChipMemory SubsystemsPeripheral SubsystemsSynthesisTiming ClosureFormal VerificationData Path Development

Qualifications

Bachelor's in Computer Science, Computer Engineering, or Related Field or Equivalent Practical Experience8+ Years Micro-Architecture and RTL Development or SoC Micro-Architecture, Design, and Integration Experience

Full job description

Summary:

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Required Skills:

ASIC Engineer, Design Responsibilities:

  1. Architecture exploration

  2. Micro-architecture development

  3. Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug

  4. Collaboration with implementation team to close the design on timing and power

Minimum Qualifications:

Minimum Qualifications:

  1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

  2. 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration

  3. RTL development using Verilog, System Verilog and HLS

Preferred Qualifications:

Preferred Qualifications:

  1. Experience in CPU, NOC, Memory and Peripheral Subsystems

  2. Experience with Synthesis, Timing Closure and Formal Verification Methodology

  3. Experience in data path development

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].

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