Principal Research Scientist (10147)

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet. Qorvo is seeking a Principal Research Scientist to serve as a principal investigator and key individual contributor leading the development of next-generation wafer-level interconnects (BEOL), wafer-level packaging (WLP) approaches, and heterogeneous integration technologies. The ideal candidate is a demonstrated leader with a track record of innovation, proposal development, and successful funding capture, as well as experience guiding small RandD teams to deliver focused, high-impact results. This role requires driving the creation of transformational, differentiated integrated circuit and packaging technologies that enable new product capabilities, accelerate technology adoption, and contribute directly to Qorvos commercial success. The candidate will work closely with internal product teams, external partners, government sponsors, and senior leadership, to shape technology roadmaps and transition research concepts into manufacturable solutions. Responsibilities: - Serve as a key individual contributor and technical leader driving next-generation wafer-level interconnect, BEOL, WLP, and heterogeneous integration research - Author and influence technology roadmaps aligned to long-term product and innovation strategies - Lead proposal development, technical shaping, capture, and execution of funded programs as Principal Investigator - Provide technical project leadership, including planning, execution, risk management, and milestone delivery - Drive hands-on process ideation, development, pathfinding, troubleshooting, and execution for wafer and wafer-level packaging technologies - Collaborate with and direct technicians, junior engineers, and process engineers to execute development activities efficiently - Communicate program status, technical results, and strategic recommendations to senior leadership, customers, and external stakeholders - Generate valuable intellectual property, including patents, invention disclosures, and proprietary process know-how - Mentor and develop junior engineers and researchers while fostering technical excellence across the team Minimum Qualifications (need-to-have): - Ph.D. in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, Physics, or a related technical field - 8+ years of hands-on semiconductor RandD experience in cleanroom fabrication environments - Demonstrated expertise in semiconductor BEOL processing and/or wafer-level packaging (WLP) technologies - Hands-on experience with advanced metallization, dielectric integration, and interconnect process development - Proven ability to lead and guide small, multidisciplinary RandD teams - Strong written and verbal communication skills, including proposal development, technical reporting, and executive-level presentations Preferred Qualifications (nice-to-have): - 3+ years of experience serving as a Principal Investigator, technical lead, or equivalent leader for advanced RandD programs - GaN RF transistor fabrication experience - Working knowledge of device and mask layout design, particularly for analog and RF applications - Experience leading or executing RandD programs sponsored by U.S. Government agencies such as DARPA, AFRL, or similar organizations - Expertise i advanced packaging and 3D heterogeneous integration (3DHI) technologies - Hands-on experience with semiconductor process modules such as lithography (stepper and/or e-beam), etch, metallization, CMP, and SEM/FIB analysis - Experience with wafer-level and chip-level integration processes, including wafer-to-wafer and die-to-wafer bonding, Cu-Cu hybrid bonding, wafer thinning, lap/grind, and TSV technologies - Experience with device processing and DC/RF characterization, including RF measurements such as S-parameters and load-pull - Familiarity with epitaxial design or close collaboration with epitaxy teams - Experience using data analytics and visualization tools such as Spotfire - Knowledge of device reliability testing, failure analysis, and root cause investigation ::: {style="color: #000000; background-color: #ffffff; margin: 0in 0in "} :::