Physical Design/Implementation Engineer-Staff

General Summary: Experience: 5 to 10 years of hands-on experience in Synthesis, Place and Route (PnR), Physical Design, and Timing/Power Signoff. Job Role - Should have strong understanding and in-depth knowledge of Physical Synthesis, and methodologies, Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, with leading industry standard tools able to work across the synthesis-to-PnR boundary to drive end-to-end PPA optimization rather than treat it as a handoff. - Hands-on experience on advanced technology nodes, including node-specific challenges around double/multi-patterning, pin access, cell legalization, and advanced DRC rules. - Experience with writing and tuning timing constraints for synthesis, STA, timing closure, and pipelining at different levels for performance optimization and carrying that intent cleanly through to physical closure. - Primary focus on driving PPA activities: aggressive area recovery, leakage/dynamic power reduction, and Fmax/performance pushes, balancing trade-offs across synthesis QoR and physical implementation. - Experience in all aspects of timing closure for multi-clock domain, multi-corner multi-mode (MCMM) designs, both at synthesis and at the physical design stage. - Should have good understanding of low-power design implementation using UPF, including power gating, multi-voltage domains, and level shifter/isolation cell placement/routing. - Experience with different power optimization flows/techniques across synthesis and PD such as clock gating, cell sizing, Vt swapping, and buffer/inverter insertion/optimization. Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Preferred Qualifications: Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. 6+ years of ASIC design, verification, validation, integration, or related work experience. 2 + years of experience with architecture and design tools. 2 + years of experience with scripting tools and programming languages. 2 + years of experience with design verification methods. 1 + year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above). Skill Set - Proficiency in Python/Tcl and AI Usage. Familiarity with standard software engineering practices like Version Control, Configuration Management, and Regression. - Familiar with PnR tools (Innovus/ICC2) and Synthesis tools (Fusion Compiler/Genus), with the ability to move fluidly between both to close PPA. - Proven hands-on experience on advanced nodes , with awareness of node-specific PPA levers and physical constraints. - Fair knowledge of Static Timing Analysis (PrimeTime/Tempus), LEC, and Low Power (LP) signoff tools. - Proficient in VLSI front-end and back-end design steps Synthesis, QoR optimization, floorplanning, placement, CTS, routing, and Equivalence Checking. - Strong PPA mindset comfortable owning power, performance, and area metrics as primary KPIs. -Knowledge of computer architecture and experience in high-speed, low-power processor design will be a plus. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm's toll-free number found here. Upon request,