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ASIC Engineer, Implementation - CAD

Meta

Austin, TXJob$114–172K/yrSeen 1 day agoSeen in employer's feed 1 day ago

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At a glance

Compensation
$114–172K/yr
Location
Austin, TX
Work Authorization
Not specified

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Job overview

Meta seeks an ASIC Implementation Engineer for its Infrastructure Silicon team, building custom silicon for data center applications. The role develops and maintains CAD methodologies, flows, and automation supporting ASIC implementation from RTL through physical design signoff. The engineer partners with design, physical design, and verification teams to enable efficient, high-quality tape-outs of next-generation infrastructure chips.

Skills & qualifications

RequiredNice to have

Skills

PythonCAD/EDA Tool DevelopmentRTL SynthesisPhysical DesignPPA OptimizationASIC ToolsCross-Functional CollaborationVendor CollaborationTiming, Area, and Power DebuggingDEF and NetlistsFloorplanning DataPin Definition GenerationPG-Aware Pin PlacementData Structures and AlgorithmsComputational GeometryPerformance OptimizationMulti-Chiplet ConnectivityFeedthrough EvaluationClock, Voltage, and Reset Domains2.5D/3D SoIC AssemblyDesign Format ParsingWeb Application DevelopmentInteractive VisualizationClient-Server ArchitectureSession and State Management

Qualifications

Bachelor's in Computer Science, Computer Engineering, or Related Field or Equivalent Experience2+ Years Synthesis and Physical Design Experience

Full job description

Summary:

Meta is seeking an ASIC Implementation Engineer to join our Infrastructure Silicon team, focused on building custom silicon for data center applications. In this role, you will develop and maintain CAD methodologies, flows, and automation scripts that support front-end and back-end ASIC implementation, from RTL through physical design signoff. You will work closely with design, physical design, and verification engineers to enable efficient, high-quality tape-outs of Meta's next-generation infrastructure chips.

Required Skills:

ASIC Engineer, Implementation - CAD Responsibilities:

  1. Design, develop and maintain production-level CAD platforms and web-based design tooling for interactive silicon architecture exploration, floorplan visualization and automated engineering analysis

  2. Build runtime-optimized data models, algorithms and Python APIs for large-scale design data — netlist, LEF/DEF, pin/track and connectivity databases — delivering order-of-magnitude runtime improvements over native EDA solutions

  3. Develop tooling for generating SOC floorplans at chip, subsystem, and block level, and drive early floorplan exploration, block shaping, and area/dimension estimation to bridge architecture and implementation

  4. Develop debug features for logical and physical connectivity and beachfront analysis on DEF and netlist data — evaluating pin locations, port configurations and connectivity consistency — including pipe/shim and feedthrough insertion for timing and area optimization

  5. Develop automation and methodology across all FE tools (Synthesis, Physical Design, STA, Power, Floorplanning, Connectivity Analysis, Pin Planning), and partner with Design, DV, Architecture and Physical Design engineers on handoffs and timing/congestion/connectivity feedback

Minimum Qualifications:

Minimum Qualifications:

  1. Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta

  2. 2+ years of experience in synthesis & physical design

  3. Proficiency in Python for algorithm development, engineering analysis, and automation

  4. Experience developing CAD/EDA tools, flows, or engineering automation

  5. Experience with RTL synthesis, physical design and PPA optimization, and knowledge of front-end and back-end ASIC tools

  6. Experience working across cross-functional teams and vendors to debug timing, area, and power issues

Preferred Qualifications:

Preferred Qualifications:

  1. Experience with DEF, netlists, floorplanning data, pin definition generation and PG-aware pin placement across hierarchical partitions

  2. Demonstrated software engineering fundamentals: data structures and algorithms, computational geometry, and performance optimization on large datasets

  3. Experience with multi-chiplet connectivity, feedthrough evaluation, clock/voltage/reset domains and 2.5D/3D SoIC assembly

  4. Experience writing parsers and data models for industry-standard design formats (Verilog netlist, LEF/DEF, Liberty, SDC)

  5. Experience building web-based engineering applications — interactive visualization frameworks, client-server architecture, session and state management

Public Compensation:

$114,000/year to $172,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].

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