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Low Power Design Engineer

Apple

San Diego, CAJobSeen 4 days agoSeen in employer's feed 4 days ago

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At a glance

Compensation
No compensation found
Location
San Diego, CA
Work Authorization
Not specified

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Requirements

Credentials this posting asks for.

Bachelor's degree

Job overview

Apple’s wireless silicon development team designs energy-efficient wireless SoCs. The Low Power Design Engineer designs power management logic for complex wireless communication SoCs and contributes to low-power logic design efforts. The role focuses on delivering functional products and requires experience in power, clock, and reset management logic, verification and debug, ASIC low-power techniques, and related design tools and methods.

Skills & qualifications

RequiredNice to have

Skills

Power Management Logic DesignVerilogPower Management Logic VerificationPower Management Logic DebugASIC Low-Power DesignCDCRDCSTAUPFShellPerlPythonSoC ComponentsProblem SolvingAnalytical SkillsSoC-Level Power Management LogicSoC Top-Level IntegrationSystem ArchitecturePost-Silicon Functional DebugPower Correlation

Qualifications

Bachelor's DegreePower Clock Reset Management Logic Track RecordPower Management Logic Verification and Debug Experience

Full job description

Role Number: 200690907-3543

Summary

Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering teams. In this highly visible role, you will be at the center of low power logic design efforts with a critical impact on getting functional products to hundreds of millions of customers quickly. Will you join us and do the work of your life here?

Description

In this role, you will be responsible for designing power management logic for complex wireless communication SoCs.

Will you join us and do the best work of your life here?

Minimum Qualifications

  • Minimum requirement of a bachelors degree.

  • Proven track record in power / clock / reset management logic design.

  • Proficiency in Verilog language.

  • Power management logic verification and debug experience.

  • Understand ASIC low power design techniques

  • Knowledge of CDC, RDC, STA and UPF.

  • Proficiency in scripting languages (Shell, Perl or Python).

  • Knowledge and experience on common SOC components, e.g. CPU, fabric, peripherals.

  • Strong problem solving and analytical skills.

Preferred Qualifications

  • SoC level power management logic experience.

  • SOC top level integration experience.

  • System architecture knowledge.

  • Post-silicon functional debug and power correlation experience.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.

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