Principal Digital IC Design Engineer (10413)

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet. We are seeking a experienced and visionary Principal ASIC Engineer to lead our next-generation silicon development. In this high-impact technical leadership role, you will own the full-flow ASIC development lifecycle, driving projects from initial architectural concepts and RTL design down to physical sign-off and silicon bring-up. The ideal candidate possesses deep expertise across both front-end design and back-end implementation, serving as a strategic authority who bridges the gap between hardware architecture, microarchitecture, and complex physical layout constraints. Key Responsibilities Technical Leadership and Strategy - Define, establish, and optimize cutting-edge ASIC design methodologies and full-flow architectures across the organization. - Act as the chief technical authority to align cross-functional domains including Architecture, RTL Design, Verification, and Physical Design. - Provide expert guidance on complex engineering trade-offs evaluating Power, Performance, and Area (PPA). Front-End Design and Architecture - Translate complex system-level product requirements into functional SoC/ASIC microarchitectures. - Write high-quality, scalable, and synthesizable hardware description code using SystemVerilog/Verilog. - Collaborate closely with Design Verification (DV) teams to review test plans and implement advanced Design for Testability (DFT) structures Back-End and Physical Implementation - Drive full chip-level and block-level execution through synthesis, floorplanning, and automated Place and Route (PandR) flows. - Formulate and sign off on rigorous Timing Constraints and execute deep Static Timing Analysis (STA) to resolve setup/hold violations. - Oversee structural physical verification including DRC, LVS, and ERC checks to guarantee tape-out readiness. Required Qualifications Education and Experience Bachelors degree in Electrical Engineering 12+ years of expe