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Principal FPGA Engineer

Butler America

Cedar Rapids, IAContract$60–71/hrSeen 1 day agoSeen in employer's feed 1 day ago

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At a glance

Compensation
$60–71/hr
Location
Cedar Rapids, IA
Schedule
Contract
Work Authorization
US work authorization required

Olive lists jobs from US employers, including remote roles you can work from the United States.

Job overview

Butler America is seeking a Principal FPGA Engineering Contractor for its Applied Research and Technology Microelectronics Technology team in Cedar Rapids. The role contributes to defense solutions by designing, implementing, verifying, and integrating high-performance digital FPGAs. The engineer will support FPGA development and reviews, collaborate in Agile planning, recommend improvements to design workflows, and provide technical leadership for project design teams.

Skills & qualifications

RequiredNice to have

Skills

VHDL/VerilogFPGA/ASIC DesignDigital Circuit ArchitectureResource TradeoffsTiming AnalysisTiming ClosureAMD/XilinxAlteraMicrochip FPGA PlatformsVivadoQuartusLiberoDebuggingTroubleshootingRevision ControlGitSubversionCommunicationTeamworkHigh-Speed Digital InterfacesDDRPCIeEthernetChip-Level VerificationConstrained Random VerificationFunctional CoverageSystemVerilogASIC/FPGA Lab ValidationLaboratory EquipmentUnixScriptingC/C++Perl

Qualifications

STEM Degree or Advanced Degree8+ Years Relevant Experience or Advanced Degree and 5+ Years5+ Years FPGA Development ExperienceUS Citizenship

Benefits

401(k) Match
Medical Insurance
Dental Insurance
Vision Insurance
Paid Time Off

Full job description

Principal FPGA Engineer

Location: Cedar Rapids, IA

Job ID: #73379

Duration: 6+months contract

Pay Range: $60-71 - W2 hourly

Job Description:

Seeking a highly skilled and innovative Principal FPGA Engineering Contractor to work with our Applied Research and Technology (ART) Microelectronics Technology team. Your work will contribute to the development of cutting-edge defense solutions across Mission Systems, leveraging your expertise in the design, implementation, verification, and integration of a wide variety of high-performance digital FPGAs.

What You Will Do:

  • Adhere to all applicable Engineering Development and Quality processes, procedures, instructions and guidelines.

  • Participate in Agile team meetings and planning activities, as required to support programs covered by this work plan.

  • Requirements, design and verification of FPGA solutions

  • Integration of developed FPGA on target hardware units

  • Supporting peer reviews and certification analysis activities

  • Peer reviewing FPGA development artifacts

  • Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow

  • Contribute to engineering estimates for new program pursuits.

  • Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status

Qualifications You Must Have:

  • Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience or an Advanced Degree in a related field and minimum 5 years of experience.

  • A minimum of 5 years professional experience in FPGA development, ASIC front end, or related areas

  • Proficient in VHDL/Verilog for FPGA/ASIC design and implementation.

  • Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure

  • Familiarity with FPGA platforms such as AMD/Xilinx, Altera, Microchip, or others, and associated toolchains (e.g., Vivado, Quartus, Libero).

  • Strong debugging and troubleshooting skills for FPGA/ASIC systems.

  • Proficiency with revision control concepts and tools (e.g., Git, Subversion)

Qualifications We Prefer:

  • Excellent communication and teamwork skills with the ability to work in a collaborative environment.

  • Experience with high-speed digital interfaces and protocols (e.g., DDR, PCIe, Ethernet).

  • Familiarity with best-practice chip-level verification techniques and languages (e.g., constrained random, functional coverage, System Verilog)

  • Experience in ASIC / FPGA lab validation using advanced laboratory equipment

  • Experience with Unix, scripting, C/C++, and/or Perl

Citizenship – US Citizen only

Benefits provided: 401K, medical, dental, and vision, sick time as applicable to state law

Butler America Aerospace, LLC. is an equal opportunity employer. Butler evaluates applicants without regard to race, color, religion, sex, age, national origin, disability, veteran status, genetic information and other legally protected characteristics. The Butler America Aerospace, LLC. EEO Policy Statement and “Know Your Rights” Poster is available here: Applicant and Employee Notices.

Butler America Aerospace, LLC. is committed to working with and providing reasonable accommodations to individuals with disabilities. If you need a reasonable accommodation because of a disability for any part of the employment process, please contact the Human Resources Department at [email protected].

How this job compares

Set against the 2,961 open Hardware Engineer jobs on Olive Jobs, counted October 29, 2026.

Pay
  • This posting$60–71/hr
  • US median$60–68/hr76 hourly ranges

This range's midpoint, $65.50/hr, is close to the US median midpoint ($64/hr) — in the middle half of Hardware Engineer hourly ranges across the US.

Openings
Olive Jobs lists 20 open Hardware Engineer jobs in Iowa and 2,961 across the US. Under 1% of them nationwide are listed as remote or flexible.
Hiring the most in Iowa
Experience
This posting asks for at least 5 years of experience; Hardware Engineer postings that state a minimum ask for 5 years at the median (2,485 postings).
Education
1,858 of the 2,961 open Hardware Engineer jobs (63%) ask for a bachelor's degree or higher.

Counted across the open, public US postings on Olive Jobs on October 29, 2026. Pay medians are the middle values of the low ends and of the high ends of postings that list both ends of a range in the same cadence (a yearly salary or an hourly rate); a range's midpoint is halfway between its ends. Pay and experience figures resting on fewer than 20 postings are left out.

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